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Fault diagnosis and logic debugging using Boolean satisfiability

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-10, Vol.24 (10), p.1606-1621

2005

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Automated Design Debugging With Abstraction and Refinement

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-10, Vol.28 (10), p.1597-1608

2009

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Incremental fault diagnosis

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-02, Vol.24 (2), p.240-251

2005

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L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture

IEEE transactions on very large scale integration (VLSI) systems, 2008-06, Vol.16 (6), p.628-638

2008

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Design error diagnosis and correction via test vector simulation

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-12, Vol.18 (12), p.1803-1816

1999

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Design rewiring using ATPG

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-12, Vol.21 (12), p.1469-1479

2002

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Path-Directed Abstraction and Refinement for SAT-Based Design Debugging

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-10, Vol.32 (10), p.1609-1622

2013

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Extraction error modeling and automated model debugging in high-performance custom designs

IEEE transactions on very large scale integration (VLSI) systems, 2006-07, Vol.14 (7), p.763-776

2006

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Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-02, Vol.31 (2), p.271-284

2012

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Two-Stage, Pipelined Register Renaming

IEEE transactions on very large scale integration (VLSI) systems, 2011-10, Vol.19 (10), p.1926-1931

2011

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Managing don't cares in Boolean satisfiability

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol.1, p.260-265 Vol.1

2004

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Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

IEEE transactions on very large scale integration (VLSI) systems, 2012-06, Vol.20 (6), p.1118-1131

2012

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On the Latency and Energy of Checkpointed Superscalar Register Alias Tables

IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.365-377

2010

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Path directed abstraction and refinement in SAT-based design debugging

DAC Design Automation Conference 2012, 2012, p.947-954

2012

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Incremental diagnosis of multiple open-interconnects

Proceedings - International Test Conference, 2002, p.1085-1092

2002

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Incremental diagnosis and correction of multiple faults and errors

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002, 2002, p.716-721

2002

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Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs

Design, Automation and Test in Europe, 2005, p.996-1001

2005

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Fault diagnosis and logic debugging using Boolean satisfiability

Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions, 2003, p.60-65

Veneris, A.

2003

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Automated debugging of SystemVerilog assertions

2011 Design, Automation & Test in Europe, 2011, p.1-6

2011

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Extraction error diagnosis and correction in high-performance designs

International Test Conference, 2003. Proceedings. ITC 2003, 2003, Vol.1, p.423-430

2003

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Design rewiring using ATPG

Proceedings - International Test Conference, 2002, p.223-232

2002

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Non-solution implications using reverse domination in a modern SAT-based debugging environment

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.629-634

2012

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Abstraction and Refinement Techniques in Automated Design Debugging

2007 Design, Automation & Test in Europe Conference & Exhibition, 2007, p.1-6

2007

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Post-verification debugging of hierarchical designs

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005, 2005, p.871-876

2005

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Design diagnosis using Boolean satisfiability

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004, p.218-223

2004

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Fault diagnosis and logic debugging using Boolean satisfiability

Automated Design Debugging With Abstraction and Refinement

Incremental fault diagnosis

L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture

Design error diagnosis and correction via test vector simulation

Design rewiring using ATPG

Path-Directed Abstraction and Refinement for SAT-Based Design Debugging

Extraction error modeling and automated model debugging in high-performance custom designs

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

Two-Stage, Pipelined Register Renaming

Managing don't cares in Boolean satisfiability

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment

On the Latency and Energy of Checkpointed Superscalar Register Alias Tables

Path directed abstraction and refinement in SAT-based design debugging

Incremental diagnosis of multiple open-interconnects

Incremental diagnosis and correction of multiple faults and errors

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs

Fault diagnosis and logic debugging using Boolean satisfiability

Automated debugging of SystemVerilog assertions

Extraction error diagnosis and correction in high-performance designs

Design rewiring using ATPG

Non-solution implications using reverse domination in a modern SAT-based debugging environment

Abstraction and Refinement Techniques in Automated Design Debugging

Post-verification debugging of hierarchical designs

Design diagnosis using Boolean satisfiability

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