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Carbon Nanotubes-Based Digitally Programmable Current Follower

VLSI design (Yverdon, Switzerland), 2018-01, Vol.2018, p.1-10

2018

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Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

IEEE transactions on electron devices, 2010-03, Vol.57 (3), p.654-664

2010

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Utilizing YOLO Models for Real-World Scenarios: Assessing Novel Mixed Defect Detection Dataset in PCBs

IEEE access, 2024, Vol.12, p.100983-100990

2024

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CSDNet: A Novel Deep Learning Framework for Improved Cataract State Detection

Diagnostics (Basel), 2024-05, Vol.14 (10), p.983

2024

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Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Semiconductor science and technology, 2024-05, Vol.39 (5), p.55001

2024

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Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

Microelectronic engineering, 2024-05, Vol.288, p.112165, Article 112165

2024

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Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

VLSI Design, 2009-01, Vol.2009, p.1-14

2009

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Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design

Journal of low power electronics and applications, 2011-07, Vol.1 (2), p.277-302

2011

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Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

IET circuits, devices & systems, 2016-11, Vol.10 (6), p.522-527

2016

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Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency

IEEE transactions on magnetics, 2022-04, Vol.58 (4), p.1-11

2022

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Chest X ray and cough sample based deep learning framework for accurate diagnosis of COVID-19

Computers & electrical engineering, 2022-10, Vol.103, p.108391-108391, Article 108391

2022

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A 128Kb RAM Design with Capacitor-Based Offset Compensation and Double-Diode based Read Assist Circuits at Low VDD

Journal of scientific & industrial research (New Delhi, India : 1963), 2020-09, Vol.79 (9)

2020

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An Energy-Efficient Hybrid Tunnel FET based STT-MRAM Memory Cell Design at Low VDD

International journal of electronics, 2022-03, Vol.109 (3), p.537-551

2022

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Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

Journal of computational electronics, 2023-02, Vol.22 (1), p.178-189

2023

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Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

International journal of circuit theory and applications, 2021-08, Vol.49 (8), p.2299-2311

2021

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Tunnel FET RF Rectifier Design for Energy Harvesting Applications

IEEE journal on emerging and selected topics in circuits and systems, 2014-12, Vol.4 (4), p.400-411

2014

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Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

International journal of circuit theory and applications, 2020-04, Vol.48 (4), p.524-538

2020

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Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator

IET circuits, devices & systems, 2020-08, Vol.14 (5), p.640-647

2020

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Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks

IET circuits, devices & systems, 2019-08, Vol.13 (5), p.689-695

2019

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Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Compact Modeling of a Generic Double-Gate MOSFET With Gate-S/D Underlap for Subthreshold Operation

IEEE transactions on electron devices, 2012-10, Vol.59 (10), p.2846-2849

2012

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The Shuttle Nanoelectromechanical Nonvolatile Memory

IEEE transactions on electron devices, 2012-04, Vol.59 (4), p.1137-1143

2012

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A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks

Microelectronics, 2023-09, Vol.139, p.105867, Article 105867

2023

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Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs

VLSI Design and Test, p.259-269

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Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

Technical review - IETE, 2018-09, Vol.35 (5), p.456-466

2018

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Carbon Nanotubes-Based Digitally Programmable Current Follower

Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

Utilizing YOLO Models for Real-World Scenarios: Assessing Novel Mixed Defect Detection Dataset in PCBs

CSDNet: A Novel Deep Learning Framework for Improved Cataract State Detection

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID): Device and Circuit Co-Design

Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

Design and Performance Benchmarking of Hybrid Tunnel FET/STT-MTJ-Based Logic In-Memory Designs for Energy Efficiency

Chest X ray and cough sample based deep learning framework for accurate diagnosis of COVID-19

A 128Kb RAM Design with Capacitor-Based Offset Compensation and Double-Diode based Read Assist Circuits at Low VDD

An Energy-Efficient Hybrid Tunnel FET based STT-MRAM Memory Cell Design at Low VDD

Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

Tunnel FET RF Rectifier Design for Energy Harvesting Applications

Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator

Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks

Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices

Compact Modeling of a Generic Double-Gate MOSFET With Gate-S/D Underlap for Subthreshold Operation

The Shuttle Nanoelectromechanical Nonvolatile Memory

A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks

Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs

Nano-scale Transistors with Circuit Interaction for Designing Energy-Efficient and Reliable Adder Cells at Low VDD

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