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Heterogeneous multiprocessor for the management of real-time video and graphics streams

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1722-1731

2000

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The complexity of multidimensional periodic scheduling

Discrete Applied Mathematics, 1998-12, Vol.89 (1), p.213-242

1998

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Constraint analysis for DSP code generation

IEEE transactions on computer-aided design of integrated circuits and systems, 1999-01, Vol.18 (1), p.44-57

1999

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A video display processing platform for future TV concepts

IEEE transactions on consumer electronics, 1999-11, Vol.45 (4), p.1230-1240

1999

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Improved force-directed scheduling in high-throughput digital signal processing

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-08, Vol.14 (8), p.945-960

1995

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Stream communication between real-time tasks in a high-performance multiprocessor

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 23-26 Feb. 1998, 1998, p.125-131

1998

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Prophid: a platform-based design method

Design automation for embedded systems, 2000-09, Vol.6 (1), p.5-37

2000

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PROPHID: a data-driven multi-processor architecture for high-performance DSP

European Design and Test Conference: Proceedings of the 1997 European conference on Design and Test; 17-20 Mar. 1997, 1997, p.611-611

1997

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Multidimensional periodic scheduling: a solution approach

European Design and Test Conference: Proceedings of the 1997 European conference on Design and Test; 17-20 Mar. 1997, 1997, p.468-468

1997

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Efficient timing constraint derivation for optimally retiming high speed processing units

Proceedings of 7th International Symposium on High-Level Synthesis, 1994, p.48-53

1994

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Efficient timing constraint derivation for optimal retiming high speed processing units

International Symposium on Systems Synthesis: Proceedings of the 7th international symposium on High-level synthesis; 18-20 May 1994, 1994, p.48-53

1994

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Allocation of multiport memories for hierarchical data stream

International Conference on Computer Aided Design: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design; 07-11 Nov. 1993, 1993, p.728-735

1993

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Consumer applications: a driving force for high-level synthesis of signal-processing architectures

IEEE MICRO, 1992-08, Vol.12 (4), p.20-33

1992

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Stream communication between real-time tasks in a high-performance multiprocessor

Proceedings Design, Automation and Test in Europe, 1998, p.125-131

1998

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Area optimization of multi-functional processing units

International Conference on Computer Aided Design: Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, 1992, p.292-299

1992

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Multidimensional periodic scheduling model and complexity

Euro-Par'96 Parallel Processing, 2005, p.226-235

2005

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Measurement of the minority-carrier transport parameters in heavily doped silicon

IEEE transactions on electron devices, 1980-05, Vol.27 (5), p.949-955

1980

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PHIDEO: a silicon compiler for high speed algorithms

European Design Automation Conference: Proceedings of the conference on European design automation; 25-28 Feb. 1991, 1991, p.436-441

1991

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A constraint driven approach to loop pipelining and register binding

Proceedings Design, Automation and Test in Europe, 1998, p.377-383

1998

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A 2-micron CMOS 8-MIPS digital signal processor with parallel processing capability

IEEE journal of solid-state circuits, 1986-10, Vol.SC-21, p.750-765

1986

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Memory synthesis for high speed DSP applications

Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, 1991, p.11.7/1-11.7/4

1991

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A 256-point discrete Fourier transform processor fabricated in a 2 μm NMOS technology

IEEE journal of solid-state circuits, 1983, Vol.18 (5), p.604-609

1983

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A 2-mum CMOS 8-MIPS digital processor with parallel processing capability

IEEE journal of solid-state circuits, 1986-10, Vol.21 (5), p.750-765

1986

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A 2-mum CMOS 10-MHz Microprogrammable Signal Processing Core With an On-Chip Multiport Memory Bank

IEEE journal of solid-state circuits, 1985-06, Vol.20 (3), p.754-760

1985

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A 2-υm CMOS 10-MHz microprogrammable signal processing core with an on-chip multiport memory bank

IEEE journal of solid-state circuits, 1985, Vol.20 (3), p.754-760

1985

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Heterogeneous multiprocessor for the management of real-time video and graphics streams

The complexity of multidimensional periodic scheduling

Constraint analysis for DSP code generation

A video display processing platform for future TV concepts

Improved force-directed scheduling in high-throughput digital signal processing

Stream communication between real-time tasks in a high-performance multiprocessor

Prophid: a platform-based design method

PROPHID: a data-driven multi-processor architecture for high-performance DSP

Multidimensional periodic scheduling: a solution approach

Efficient timing constraint derivation for optimally retiming high speed processing units

Efficient timing constraint derivation for optimal retiming high speed processing units

Allocation of multiport memories for hierarchical data stream

Consumer applications: a driving force for high-level synthesis of signal-processing architectures

Stream communication between real-time tasks in a high-performance multiprocessor

Area optimization of multi-functional processing units

Multidimensional periodic scheduling model and complexity

Measurement of the minority-carrier transport parameters in heavily doped silicon

PHIDEO: a silicon compiler for high speed algorithms

A constraint driven approach to loop pipelining and register binding

A 2-micron CMOS 8-MIPS digital signal processor with parallel processing capability

Memory synthesis for high speed DSP applications

A 256-point discrete Fourier transform processor fabricated in a 2 μm NMOS technology

A 2-mum CMOS 8-MIPS digital processor with parallel processing capability

A 2-mum CMOS 10-MHz Microprogrammable Signal Processing Core With an On-Chip Multiport Memory Bank

A 2-υm CMOS 10-MHz microprogrammable signal processing core with an on-chip multiport memory bank

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