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Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing

ACM transactions on reconfigurable technology and systems, 2019-09, Vol.12 (3), p.1-24

2019

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Ps and Qs: Quantization-Aware Pruning for Efficient Low Latency Neural Network Inference

Frontiers in artificial intelligence, 2021-07, Vol.4, p.676564-676564

2021

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LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications

2020 30th International Conference on Field-Programmable Logic and Applications (FPL), 2020, p.291-297

2020

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RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures

IEEE MICRO, 2022-11, Vol.42 (6), p.125-133

2022

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FINN- R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks

ACM transactions on reconfigurable technology and systems, 2018-12, Vol.11 (3), p.1-23

2018

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EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators

IEEE transactions on computers, 2024-09, Vol.73 (9), p.2275-2289

2024

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Random access schemes for efficient FPGA SpMV acceleration

Microprocessors and microsystems, 2016-11, Vol.47, p.321-332

2016

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Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning

ACM transactions on reconfigurable technology and systems, 2022-06, Vol.15 (2), p.1-34

2022

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Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach

IEEE transactions on computers, 2021-10, Vol.70 (10), p.1654-1669

2021

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FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017, p.65-74

2017

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An energy efficient column-major backend for FPGA SpMV accelerators

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014, p.432-439

2014

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BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018, p.307-3077

2018

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Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic

2017 IEEE International Conference on Computer Design (ICCD), 2017, p.419-422

2017

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A Vector Caching Scheme for Streaming FPGA SpMV Accelerators

Applied Reconfigurable Computing, p.15-26

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Work-in-progress: towards efficient quantized neural network inference on mobile devices

2017 International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES), 2017, p.1-2

2017

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Towards efficient quantized neural network inference on mobile devices: work-in-progress

Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, 2017, p.1-2

2017

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Scaling Binarized Neural Networks on Reconfigurable Logic

Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017, p.25-30

2017

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High-Throughput DNN Inference with LogicNets

2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2020, p.238-238

2020

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Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform

2015 25th International Conference on Field Programmable Logic and Applications (FPL), 2015, p.1-8

2015

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Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach

Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020, p.317-317

2020

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Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing

Ps and Qs: Quantization-Aware Pruning for Efficient Low Latency Neural Network Inference

LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications

RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures

FINN- R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks

EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators

Random access schemes for efficient FPGA SpMV acceleration

Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning

Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

An energy efficient column-major backend for FPGA SpMV accelerators

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic

A Vector Caching Scheme for Streaming FPGA SpMV Accelerators

Work-in-progress: towards efficient quantized neural network inference on mobile devices

Towards efficient quantized neural network inference on mobile devices: work-in-progress

Scaling Binarized Neural Networks on Reconfigurable Logic

High-Throughput DNN Inference with LogicNets

Hybrid breadth-first search on a single-chip FPGA-CPU heterogeneous platform

Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach

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