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Characterization of the ultrathin HfO2 and Hf-silicate films grown by atomic layer deposition

IEEE transactions on electron devices, 2007-04, Vol.54 (4), p.759-766

2007

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Sensing characteristics of dopamine using Pt/n-Si structure

Vacuum, 2020-02, Vol.172, p.109050, Article 109050

2020

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An Ultrathin Forming-Free HfOx Resistance Memory With Excellent Electrical Performance

IEEE electron device letters, 2010-12, Vol.31 (12), p.1473-1475

2010

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Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration

IEEE transactions on components, packaging, and manufacturing technology (2011), 2012-06, Vol.2 (6), p.956-963

2012

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Fully Symmetric 3-D Transformers With Through-Silicon via IPD Technology for RF Applications

IEEE transactions on components, packaging, and manufacturing technology (2011), 2019-11, Vol.9 (11), p.2143-2151

2019

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Low-Power Switching of Nonvolatile Resistive Memory Using Hafnium Oxide

Japanese Journal of Applied Physics, 2007-04, Vol.46 (4S), p.2175

2007

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Electrical evidence of unstable anodic interface in Ru∕HfOx∕TiN unipolar resistive memory

Applied physics letters, 2008-04, Vol.92 (14)

2008

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CMOS-compatible GaN HEMT on 200mm Si-substrate for RF application

2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, p.1-2

2021

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Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

Japanese Journal of Applied Physics, 2009-04, Vol.48 (4S), p.4

2009

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Charge-Trapping-Type Flash Memory Device With Stacked High- k Charge-Trapping Layer

IEEE electron device letters, 2009-07, Vol.30 (7), p.775-777

2009

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Plasma charging damage on MOS devices with gate insulator of high-dielectric constant material

IEEE electron device letters, 2001-11, Vol.22 (11), p.527-529

2001

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A process for high yield and high performance carbon nanotube field effect transistors

Microelectronics and reliability, 2010-05, Vol.50 (5), p.666-669

2010

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An Ultrathin Forming-Free \hbox Resistance Memory With Excellent Electrical Performance

IEEE electron device letters, 2010-12, Vol.31 (12), p.1473-1475

2010

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Feedback control of HfO2 etch processing in inductively coupled Cl2/N2/Ar plasmas

Journal of vacuum science & technology. A, Vacuum, surfaces, and films, 2008-09, Vol.26 (5), p.1282-1286

2008

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A novel SONOS-type flash device with stacked charge trapping layer

Microelectronic engineering, 2009-07, Vol.86 (7), p.1863-1865

2009

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Low-cost 3DIC process technologies for wide-I/O memory cube

2015 International Symposium on VLSI Technology, Systems and Applications, 2015, p.1-2

2015

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Plasma-charging effects on submicron MOS devices

IEEE transactions on electron devices, 2002-07, Vol.49 (7), p.1151-1157

2002

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Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

2015 International Symposium on VLSI Technology, Systems and Applications, 2015, p.1-2

2015

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Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

Solid-state electronics, 2008-10, Vol.52 (10), p.1573-1577

2008

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Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density

2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2021, p.1-2

2021

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Platinum membrane on Ti/n-Si substrate for dopamine detection

2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020, p.80-81

2020

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Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

Journal of microelectronics and electronic packaging, 2012, Vol.9 (1), p.31-36

2012

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Study on the interface thermal stability of metal-oxide-semiconductor structures by inelastic electron tunneling spectroscopy

Applied physics letters, 2006-06, Vol.88 (26), p.262909-262909-3

2006

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Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.1130-1135

2011

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Reduction of Plasma Etching Induced Electrical Degradation in Metal-Oxide-Si Capacitors by Furnace Grown Oxides Rapid Thermal Annealed in N 2 O

Japanese Journal of Applied Physics, 1997-12, Vol.36 (12A), p.L1580

1997

Volltextzugriff (PDF)

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Characterization of the ultrathin HfO2 and Hf-silicate films grown by atomic layer deposition

Sensing characteristics of dopamine using Pt/n-Si structure

An Ultrathin Forming-Free HfOx Resistance Memory With Excellent Electrical Performance

Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration

Fully Symmetric 3-D Transformers With Through-Silicon via IPD Technology for RF Applications

Low-Power Switching of Nonvolatile Resistive Memory Using Hafnium Oxide

Electrical evidence of unstable anodic interface in Ru∕HfOx∕TiN unipolar resistive memory

CMOS-compatible GaN HEMT on 200mm Si-substrate for RF application

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

Charge-Trapping-Type Flash Memory Device With Stacked High- k Charge-Trapping Layer

Plasma charging damage on MOS devices with gate insulator of high-dielectric constant material

A process for high yield and high performance carbon nanotube field effect transistors

An Ultrathin Forming-Free \hbox Resistance Memory With Excellent Electrical Performance

Feedback control of HfO2 etch processing in inductively coupled Cl2/N2/Ar plasmas

A novel SONOS-type flash device with stacked charge trapping layer

Low-cost 3DIC process technologies for wide-I/O memory cube

Plasma-charging effects on submicron MOS devices

Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

Ultra-thin Hf0.5Zr0.5O2 Ferroelectric Tunnel Junction with High Current Density

Platinum membrane on Ti/n-Si substrate for dopamine detection

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

Study on the interface thermal stability of metal-oxide-semiconductor structures by inelastic electron tunneling spectroscopy

Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers

Reduction of Plasma Etching Induced Electrical Degradation in Metal-Oxide-Si Capacitors by Furnace Grown Oxides Rapid Thermal Annealed in N 2 O

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