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Soft error interception latch: double node charge sharing SEU tolerant design

Electronics letters, 2015-02, Vol.51 (4), p.330-332

2015

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A Stress-Relaxed Negative Voltage-Level Converter

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2007-03, Vol.54 (3), p.282-286

Tsiatouhas, Y.E.

2007

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A Robust and Reconfigurable Multi-mode Power Gating Architecture

2011 24th Internatioal Conference on VLSI Design, 2011, p.280-285

2011

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A Design Technique for Energy Reduction in NORA CMOS Logic

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-12, Vol.53 (12), p.2647-2655

2006

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Testable Designs of Multiple Precharged Domino Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2007-04, Vol.15 (4), p.461-465

2007

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A Built-In Voltage Measurement Technique for the Calibration of RF Mixers

IEEE transactions on instrumentation and measurement, 2013-04, Vol.62 (4), p.732-742

2013

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A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

Journal of electronic testing, 2004-10, Vol.20 (5), p.523-531

2004

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A design for testability technique for mixed-signal differential circuits

Journal of physics. Conference series, 2005-01, Vol.10 (1), p.348-351

2005

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A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators

Journal of electronic testing, 2004-04, Vol.20 (2), p.133-142

2004

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A high-density DRAM cell with built-in gain stage

IEEE transactions on electron devices, 2001-06, Vol.48 (6), p.1194-1199

2001

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Optimized built-in self-calibration of RF SoCs

2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2016, p.1-4

2016

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Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers

International journal of electronics, 2003-02, Vol.90 (2), p.145-158

2003

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Timing error tolerance in nanometer ICs

2010 IEEE 16th International On-Line Testing Symposium, 2010, p.283-288

2010

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Management of charge pump circuits

Integration (Amsterdam), 2000-11, Vol.30 (1), p.91-101

2000

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A Current Mode, Parallel, Two-Rail Code Checker

IEEE transactions on computers, 2008-08, Vol.57 (8), p.1032-1045

2008

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Single event upset tolerance in flip-flop based microprocessor cores

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2012, p.79-84

2012

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Design of stuck-open fault testable CMOS complex gates

Electronics letters, 1996, Vol.32 (4), p.315

1996

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Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches

2011 Sixteenth IEEE European Test Symposium, 2011, p.13-18

2011

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Path delay fault testing of multiplexer-based shifters

International journal of electronics, 2001-08, Vol.88 (8), p.923-937

2001

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High fan-in differential current mirror logic

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.

2006

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Low Power and High Speed Static CMOS Digital Magnitude Comparators

2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018, p.249-252

2018

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C-testable one-dimensional ILAs with respect to path delay faults: theory and applications

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223), 1998, p.155-163

1998

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Robust test generation for transistor stuck-open faults in CMOS complex gates

International journal of electronics, 1995-08, Vol.79 (2), p.129-142, Article 129

1995

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Improved alternate test accuracy using weighted training sets

2016 Conference on Design of Circuits and Integrated Systems (DCIS), 2016, p.1-6

2016

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Hierarchical robust test generation for CMOS circuit stuck-open faults

International journal of electronics, 1997-01, Vol.82 (1), p.45-60

1997

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Soft error interception latch: double node charge sharing SEU tolerant design

A Stress-Relaxed Negative Voltage-Level Converter

A Robust and Reconfigurable Multi-mode Power Gating Architecture

A Design Technique for Energy Reduction in NORA CMOS Logic

Testable Designs of Multiple Precharged Domino Circuits

A Built-In Voltage Measurement Technique for the Calibration of RF Mixers

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

A design for testability technique for mixed-signal differential circuits

A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators

A high-density DRAM cell with built-in gain stage

Optimized built-in self-calibration of RF SoCs

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers

Timing error tolerance in nanometer ICs

Management of charge pump circuits

A Current Mode, Parallel, Two-Rail Code Checker

Single event upset tolerance in flip-flop based microprocessor cores

Design of stuck-open fault testable CMOS complex gates

Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches

Path delay fault testing of multiplexer-based shifters

High fan-in differential current mirror logic

Low Power and High Speed Static CMOS Digital Magnitude Comparators

C-testable one-dimensional ILAs with respect to path delay faults: theory and applications

Robust test generation for transistor stuck-open faults in CMOS complex gates

Improved alternate test accuracy using weighted training sets

Hierarchical robust test generation for CMOS circuit stuck-open faults

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