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Linkage, whole genome sequence, and biological data implicate variants in RAB10 in Alzheimer's disease resilience

Genome medicine, 2017-11, Vol.9 (1), p.100-100, Article 100

2017

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Problems

Mathematics magazine, 1976-03, Vol.49 (2), p.95

1976

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Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Journal of low power electronics and applications, 2020-06, Vol.10 (2), p.16

2020

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Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

IEEE transactions on very large scale integration (VLSI) systems, 2021-05, Vol.29 (5), p.843-856

2021

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1536-1543

2004

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2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.22-23

2022

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A Digital LDO in 22nm CMOS with a 4b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework

IEEE solid-state circuits letters, 2023-04, p.1-1

2023

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A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework

IEEE solid-state circuits letters, 2023, Vol.6, p.101-104

2023

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Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Annual ACM IEEE Design Automation Conference: Proceedings of the 39th conference on Design automation : New Orleans, Louisiana, USA; 10-14 June 2002, 2002, p.486-491

2002

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LINKAGE AND WHOLE GENOME SEQUENCE ANALYSIS OF ALZHEIMER'S DISEASE RESILIENCE AND RISK

Alzheimer's & dementia, 2016-07, Vol.12 (7), p.P675-P675

2016

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P2‐158: LINKAGE AND WHOLE GENOME SEQUENCE ANALYSIS OF ALZHEIMER'S DISEASE RESILIENCE AND RISK

Alzheimer's & dementia, 2016-07, Vol.12 (7S_Part_14), p.P675-P675

2016

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On-Chip High-Resolution Timing Characterization Circuits for Memory IPs

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022, p.377-380

2022

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Comparative analysis of conventional and statistical design techniques

2007 44th ACM/IEEE Design Automation Conference, 2007, p.238-243

2007

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A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022, p.2-4

2022

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Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1536-1543

2004

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A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302), 2002, p.320-321

2002

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Design optimizations of a high performance microprocessor using combinations of Dual-VT allocation and transistor sizing

2002

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Linkage, whole genome sequence, and biological data implicate variants in RAB10 in Alzheimer's disease resilience

Problems

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

Correction to: Linkage, whole genome sequence, and biological data implicate variants in RAB10 in Alzheimer's disease resilience

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process

2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators

A Digital LDO in 22nm CMOS with a 4b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework

A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

LINKAGE AND WHOLE GENOME SEQUENCE ANALYSIS OF ALZHEIMER'S DISEASE RESILIENCE AND RISK

P2‐158: LINKAGE AND WHOLE GENOME SEQUENCE ANALYSIS OF ALZHEIMER'S DISEASE RESILIENCE AND RISK

On-Chip High-Resolution Timing Characterization Circuits for Memory IPs

Comparative analysis of conventional and statistical design techniques

A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework

Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process

A leakage-tolerant dynamic register file using leakage bypass with stack forcing (LBSF) and source follower NMOS (SFN) techniques

Design optimizations of a high performance microprocessor using combinations of Dual-VT allocation and transistor sizing

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