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Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

IEEE journal of solid-state circuits, 2009-01, Vol.44 (1), p.49-63

2009

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Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1396-1402

2002

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Dynamic sleep transistor and body bias for active leakage power control of microprocessors

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1838-1845

2003

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Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

IEEE journal of solid-state circuits, 2003-05, Vol.38 (5), p.826-829

2003

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Formal derivation of optimal active shielding for low-power on-chip buses

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-05, Vol.25 (5), p.821-836

2006

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A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

IEEE journal of solid-state circuits, 2003-11, Vol.38 (11), p.1866-1875

2003

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Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-09, Vol.53 (9), p.1928-1933

2006

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Impact of Parameter Variations on Circuits and Microarchitecture

IEEE MICRO, 2006-11, Vol.26 (6), p.30-39

2006

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Refueling: Preventing Wire Degradation due to Electromigration

IEEE MICRO, 2008-11, Vol.28 (6), p.37-46

2008

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A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuits

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008, p.343-351

2008

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Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.155-158

2008

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5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1421

2002

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1536-1543

2004

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9)

2004

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Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1536-1543

2004

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Comparative analysis of conventional and statistical design techniques

2007 44th ACM/IEEE Design Automation Conference, 2007, p.238-243

2007

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5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1421-1432

2002

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Leakage and process variation effects in current testing on future CMOS circuits

IEEE design & test of computers, 2002-09, Vol.19 (5), p.36-43

2002

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Competing Institutional Logics and Paradoxical Universalism: School-to-Work Transitions of Disabled Youth in Switzerland and the United States

Social inclusion, 2020-01, Vol.8 (1), p.155-167

2020

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Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

Dynamic sleep transistor and body bias for active leakage power control of microprocessors

Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors

Formal derivation of optimal active shielding for low-power on-chip buses

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques

Impact of Parameter Variations on Circuits and Microarchitecture

Refueling: Preventing Wire Degradation due to Electromigration

A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuits

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process

Measurements and analysis of SER-tolerant latch in a 90-nm Dual-VT CMOS process

Comparative analysis of conventional and statistical design techniques

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

Leakage and process variation effects in current testing on future CMOS circuits

Competing Institutional Logics and Paradoxical Universalism: School-to-Work Transitions of Disabled Youth in Switzerland and the United States

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