UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

IEEE transactions on electron devices, 2006-09, Vol.53 (9), p.2370-2377

2006

Volltextzugriff (PDF)

Novel high-density low-power logic circuit techniques using DG devices

IEEE transactions on electron devices, 2005-10, Vol.52 (10), p.2339-2342

2005

Volltextzugriff (PDF)

Double gate (DG)-SOI ratioed logic with symmetric DG load––a novel approach for sub 50 nm low-voltage/low-power circuit design

Solid-state electronics, 2004-10, Vol.48 (10), p.1727-1732

2004

Volltextzugriff (PDF)

High-density logic techniques with reduced-stack double-gate MOSFETs

2005 IEEE International SOI Conference Proceedings, 2005, p.85-86

2005

Volltextzugriff (PDF)

An all digital frequency-locked loop immune to hysteresis effects for power management of multicore processors

2010 IEEE International SOI Conference (SOI), 2010, p.1-2

2010

Volltextzugriff (PDF)

Metastability of SOI CMOS latches

International journal of electronics, 1999-07, Vol.86 (7), p.807-813

1999

Volltextzugriff (PDF)

Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, 2005, p.235-238

2005

Volltextzugriff (PDF)

CMOS transistor sizing for minimization of energy-delay product

Great Lakes Symposium on VLSI: Proceedings of the 6th Great Lakes Symposium on VLSI; 22-23 Mar. 1996, 1996, p.168-173

1996

Volltextzugriff (PDF)

Novel high-density low-power high-performance double-gate logic techniques

2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 2004, p.122-123

2004

Volltextzugriff (PDF)

Optimal Design of Nanoscale Triple-Gate Devices

2006 IEEE international SOI Conferencee Proceedings, 2006, p.143-144

2006

Volltextzugriff (PDF)

Low voltage/low power sub 50 nm double gate SOI ratioed logic

2003 IEEE International Conference on SOI, 2003, p.177-178

2003

Volltextzugriff (PDF)

Assessing circuit level impact of self-heating in 0.13 /spl mu/m SOI CMOS

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2001, p.101-102

2001

Volltextzugriff (PDF)

Pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125), 2000, p.26-27

2000

Volltextzugriff (PDF)

Performance comparison of differential static CMOS circuit topologies in SOI technology

1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199), 1998, p.123-124

1998

Volltextzugriff (PDF)

Metastability of SOI CMOS latches

1997 IEEE International SOI Conference Proceedings, 1997, p.162-163

1997

Volltextzugriff (PDF)

Conservative modeling of the contribution of spurious transitions to power dissipation in digital CMOS VLSI circuits

Proceedings of the 39th Midwest Symposium on Circuits and Systems, 1996, Vol.1, p.317-320 vol.1

1996

Volltextzugriff (PDF)

Single Polysilicon Gate High-Density Logic Using Independently-Controlled Double-Gate Devices

2005 IEEE Asian Solid-State Circuits Conference, 2005, p.353-356

2005

Volltextzugriff (PDF)

DG-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm LV/LP circuit design

International Semiconductor Device Research Symposium, 2003, 2003, p.390-391

2003

Volltextzugriff (PDF)

Comparison of a wide range of differential CMOS logic topologies

Proceedings of the 39th Midwest Symposium on Circuits and Systems, 1996, Vol.1, p.179-182 vol.1

1996

Volltextzugriff (PDF)

An efficient macromodel for static CMOS multi-port memories

Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 1993, p.8.2.1-8.2.4

1993

Volltextzugriff (PDF)

Hysteresis in floating-body PD/SOI CMOS circuits

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453), 1999, p.278-281

1999

Volltextzugriff (PDF)

1 – 21 von 21

Menü

Weitere Dienste

Einstellungen

High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices

Novel high-density low-power logic circuit techniques using DG devices

Double gate (DG)-SOI ratioed logic with symmetric DG load––a novel approach for sub 50 nm low-voltage/low-power circuit design

High-density logic techniques with reduced-stack double-gate MOSFETs

An all digital frequency-locked loop immune to hysteresis effects for power management of multicore processors

Metastability of SOI CMOS latches

Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor

CMOS transistor sizing for minimization of energy-delay product

Novel high-density low-power high-performance double-gate logic techniques

Optimal Design of Nanoscale Triple-Gate Devices

Low voltage/low power sub 50 nm double gate SOI ratioed logic

Assessing circuit level impact of self-heating in 0.13 /spl mu/m SOI CMOS

Pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design

Performance comparison of differential static CMOS circuit topologies in SOI technology

Metastability of SOI CMOS latches

Conservative modeling of the contribution of spurious transitions to power dissipation in digital CMOS VLSI circuits

Single Polysilicon Gate High-Density Logic Using Independently-Controlled Double-Gate Devices

DG-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm LV/LP circuit design

Comparison of a wide range of differential CMOS logic topologies

An efficient macromodel for static CMOS multi-port memories

Hysteresis in floating-body PD/SOI CMOS circuits

Suchergebnisse filtern