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On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1323-1335

2023

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Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance

IEEE transactions on very large scale integration (VLSI) systems, 2017-09, Vol.25 (9), p.2434-2448

2017

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A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.784-788

2016

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Cost-effective reliability enhancement for video stitching applications based on error-tolerance

Microelectronics and reliability, 2024-04, Vol.155, p.115364, Article 115364

2024

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Test Response Compaction via Output Bit Selection

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-10, Vol.30 (10), p.1534-1544

2011

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A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosability

2017 International Test Conference in Asia (ITC-Asia), 2017, p.52-57

2017

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An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-08, Vol.32 (8), p.1254-1264

2013

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Error-Tolerability Evaluation and Test for Images in Face Detection Applications

2017 IEEE 26th Asian Test Symposium (ATS), 2017, p.206-211

2017

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Cost-effective memory protection and reliability evaluation based on machine error-tolerance: A case study on no-accuracy-loss YOLOv4 object detection model

Microelectronics and reliability, 2023-08, Vol.147, p.115039, Article 115039

2023

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An Error Rate Based Test Methodology to Support Error-Tolerance

IEEE transactions on reliability, 2008-03, Vol.57 (1), p.204-214

2008

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On Probability of Detection Lossless Concurrent Error Detection Based on Implications

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-05, Vol.37 (5), p.1090-1103

2018

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Counter-Based Output Selection for Test Response Compaction

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-01, Vol.32 (1), p.152-164

2013

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An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-06, Vol.30 (6), p.930-934

2011

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An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications

ACM transactions on design automation of electronic systems, 2020-01, Vol.25 (1), p.1-27

2020

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Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-02, Vol.37 (2), p.485-498

2018

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A no-reference error-tolerability test technique for videos via edge and extreme-value checking and its hardware implementation

Microelectronics and reliability, 2019-08, Vol.99, p.1-11

2019

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On-Chip SOC Test Platform Design Based on IEEE 1500 Standard

IEEE transactions on very large scale integration (VLSI) systems, 2010-07, Vol.18 (7), p.1134-1139

2010

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An Efficient Test Methodology for Image Processing Applications Based on Error-Tolerance

2013 22nd Asian Test Symposium, 2013, p.289-294

2013

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Cost-Effective Error-Mitigation for High Memory Error Rate of DNN: A Case Study on YOLOv4

2023 IEEE International Test Conference in Asia (ITC-Asia), 2023, p.1-6

2023

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Error-tolerability enhancement via bit inversion and median filtering for single-bit errors in image processing circuits

Microsystem technologies : sensors, actuators, systems integration, 2018, Vol.24 (1), p.59-69

2018

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On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian Detection

2020 IEEE 38th VLSI Test Symposium (VTS), 2020, p.1-6

2020

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Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-05, Vol.31 (5), p.754-764

2012

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Efficient LFSR Reseeding Based on Internal-Response Feedback

Journal of electronic testing, 2014-12, Vol.30 (6), p.673-685

2014

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Accumulator-based output selection for test response compaction

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.2313-2316

2012

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Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation

Journal of electronic testing, 2014-12, Vol.30 (6), p.687-699

2014

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On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images

Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance

A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies

Cost-effective reliability enhancement for video stitching applications based on error-tolerance

Test Response Compaction via Output Bit Selection

A hybrid concurrent error detection scheme for simultaneous improvement on probability of detection and diagnosability

An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters

Error-Tolerability Evaluation and Test for Images in Face Detection Applications

Cost-effective memory protection and reliability evaluation based on machine error-tolerance: A case study on no-accuracy-loss YOLOv4 object detection model

An Error Rate Based Test Methodology to Support Error-Tolerance

On Probability of Detection Lossless Concurrent Error Detection Based on Implications

Counter-Based Output Selection for Test Response Compaction

An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement

An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications

Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications

A no-reference error-tolerability test technique for videos via edge and extreme-value checking and its hardware implementation

On-Chip SOC Test Platform Design Based on IEEE 1500 Standard

An Efficient Test Methodology for Image Processing Applications Based on Error-Tolerance

Cost-Effective Error-Mitigation for High Memory Error Rate of DNN: A Case Study on YOLOv4

Error-tolerability enhancement via bit inversion and median filtering for single-bit errors in image processing circuits

On Classification of Acceptable Images for Reliable Artificial Intelligence Systems: A Case Study on Pedestrian Detection

Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement

Efficient LFSR Reseeding Based on Internal-Response Feedback

Accumulator-based output selection for test response compaction

Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation

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