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Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

IEEE MICRO, 2013-07, Vol.33 (4), p.35-45

2013

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Introducing the Adaptive Energy Management Features of the Power7 Chip

IEEE MICRO, 2011-03, Vol.31 (2), p.60-75

2011

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A 28 GHz Hybrid PLL in 32 nm SOI CMOS

IEEE journal of solid-state circuits, 2014-04, Vol.49 (4), p.1027-1035

2014

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A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

IEEE journal of solid-state circuits, 2013-05, Vol.48 (5), p.1138-1150

2013

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A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.3220-3231

2012

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An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.996-1008

2013

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An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

IEEE transactions on very large scale integration (VLSI) systems, 2010-07, Vol.18 (7), p.1043-1056

2010

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A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.42-51

2008

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Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing"

IEEE journal of solid-state circuits, 2013-06, Vol.48 (6), p.1539-1539

2013

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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, p.1-4

2011

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A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

2015

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Integrated transversal equalizers in high-speed fiber-optic systems

IEEE journal of solid-state circuits, 2003-12, Vol.38 (12), p.2131-2137

2003

Volltextzugriff (PDF)

Active management of timing guardband to save energy in POWER7

2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2011, p.1-11

2011

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Performance of Simulated Annealing Algorithm in Equalized Multimode Fiber Links With Linear Equalizers

Journal of lightwave technology, 2006-11, Vol.24 (11), p.4235-4249

2006

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A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2013-08, Vol.60 (8), p.2009-2017

2013

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A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

2015

Volltextzugriff (PDF)

Message from the Chairs

11th IEEE International Symposium on Asynchronous Circuits and Systems, 2005, p.vii-viii

2005

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Asynchronous parallel prefix computation

IEEE transactions on computers, 1998-11, Vol.47 (11), p.1244-1252

1998

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A 100-MIPS GaAs asynchronous microprocessor

IEEE design & test of computers, 1994, Vol.11 (2), p.43-49

1994

Volltextzugriff (PDF)

Asynchronous circuits and systems in superconducting RSFQ digital technology

Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1998, p.274-285

1998

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Global diversity of stoneflies (Plecoptera; Insecta) in freshwater

Hydrobiologia, 2008-01, Vol.595 (1), p.365-377

2008

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Magnetically tunable bidirectional locomotion of a self-assembled nanorod-sphere propeller

Nature communications, 2018-04, Vol.9 (1), p.1663-7, Article 1663

2018

Volltextzugriff (PDF)

What do caprellids (Crustacea: Amphipoda) feed on

Marine biology, 2009-08, Vol.156 (9), p.1881-1890

2009

Volltextzugriff (PDF)

A bibliometric overview of the Journal of Business Research between 1973 and 2014

Journal of business research, 2015-12, Vol.68 (12), p.2645-2653

2015

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Seasonality, species richness and poor dispersion mediate intraspecific trait variability in stonefly community responses along an elevational gradient

Freshwater biology, 2017-05, Vol.62 (5), p.916-928

2017

Volltextzugriff (PDF)

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Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

Introducing the Adaptive Energy Management Features of the Power7 Chip

A 28 GHz Hybrid PLL in 32 nm SOI CMOS

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing"

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Integrated transversal equalizers in high-speed fiber-optic systems

Active management of timing guardband to save energy in POWER7

Performance of Simulated Annealing Algorithm in Equalized Multimode Fiber Links With Linear Equalizers

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Message from the Chairs

Asynchronous parallel prefix computation

A 100-MIPS GaAs asynchronous microprocessor

Asynchronous circuits and systems in superconducting RSFQ digital technology

Global diversity of stoneflies (Plecoptera; Insecta) in freshwater

Magnetically tunable bidirectional locomotion of a self-assembled nanorod-sphere propeller

What do caprellids (Crustacea: Amphipoda) feed on

A bibliometric overview of the Journal of Business Research between 1973 and 2014

Seasonality, species richness and poor dispersion mediate intraspecific trait variability in stonefly community responses along an elevational gradient

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