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Using Sidereal Rotation Period Expressions to Calculate the Sun’s Rotation Period through Observation of Sunspots

Mathematical problems in engineering, 2015-01, Vol.2015, p.1-4

2015

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Corrigendum to “Using Sidereal Rotation Period Expressions to Calculate the Sun’s Rotation Period through Observation of Sunspots”

Mathematical problems in engineering, 2017-01, Vol.2017 (1)

2017

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The dynamical behavior of self-mixing by Doppler feedback in single-mode microchip Nd:YAG laser

2016 International Conference on Advanced Materials for Science and Engineering (ICAMSE), 2016, p.245-247

2016

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Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

2016 IEEE International Reliability Physics Symposium (IRPS), 2016, p.EL-3-1-EL-3-4

2016

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ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.EL.3.1-EL.3.4

2013

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Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

2009 IEEE International Conference on IC Design and Technology, 2009, p.21-24

2009

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Latch-up free ESD protection design with SCR structure in advanced CMOS technology

2011 International Reliability Physics Symposium, 2011, p.4C.3.1-4C.3.4

2011

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High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

2008 IEEE International Reliability Physics Symposium, 2008, p.627-628

2008

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Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.594-595

2007

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Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process

IEEE electron device letters, 2003-03, Vol.24 (3), p.168-170, Article 168

2003

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Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2017, p.1-3

2017

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The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

2011 International Reliability Physics Symposium, 2011, p.EL.1.1-EL.1.3

2011

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Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application

Solid state electronics letters, 2019-01, Vol.1 (1), p.25-29

2019

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ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

2006 IEEE International Integrated Reliability Workshop Final Report, 2006, p.167-170

2006

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The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007, p.249-252

2007

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ESD protection design with lateral DMOS transistor in 40-V BCD technology

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2010, p.1-4

2010

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Image-based detection and obstacle avoidance for mobile robots

2009 4th International Conference on Autonomous Robots and Agents, 2009, p.193-197

2009

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Investigation of a SiGe HBT during ESD stress in a 0.18-mum SiGe BiCMOS process

IEEE electron device letters, 2003-03, Vol.24 (3), p.168-170

2003

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Investigation of a SiGe HBT during ESD stress in a 0.18-[micro]m SiGe BiCMOS process

IEEE electron device letters, 2003-03, Vol.24 (3), p.168

2003

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Investigation of a SiGe HBT during ESD stress in a 0.18-micron SiGe BiCMOS process

IEEE electron device letters, 2003-03, Vol.24 (3), p.168-170

2003

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Advances in Spatial and Temporal Databases: 15th International Symposium, SSTD 2017, Arlington, VA, USA, August 21 - 23, 2017, Proceedings

1, 2017

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Using Sidereal Rotation Period Expressions to Calculate the Sun’s Rotation Period through Observation of Sunspots

Corrigendum to “Using Sidereal Rotation Period Expressions to Calculate the Sun’s Rotation Period through Observation of Sunspots”

The dynamical behavior of self-mixing by Doppler feedback in single-mode microchip Nd:YAG laser

Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Latch-up free ESD protection design with SCR structure in advanced CMOS technology

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process

Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application

ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Image-based detection and obstacle avoidance for mobile robots

Investigation of a SiGe HBT during ESD stress in a 0.18-mum SiGe BiCMOS process

Investigation of a SiGe HBT during ESD stress in a 0.18-[micro]m SiGe BiCMOS process

Investigation of a SiGe HBT during ESD stress in a 0.18-micron SiGe BiCMOS process

Advances in Spatial and Temporal Databases: 15th International Symposium, SSTD 2017, Arlington, VA, USA, August 21 - 23, 2017, Proceedings

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