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Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

2016 IEEE International Reliability Physics Symposium (IRPS), 2016, p.EL-3-1-EL-3-4

2016

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Lower trigger voltage design for ESD protection device applied in PMIC application

2014 IEEE International Reliability Physics Symposium, 2014, p.EL.3.1-EL.3.4

2014

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ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.EL.3.1-EL.3.4

2013

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Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices

IEEE transactions on electron devices, 2004-05, Vol.51 (5), p.708-713

2004

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Low-leakage diode string designs using triple-well technologies for RF-ESD applications

IEEE electron device letters, 2003-09, Vol.24 (9), p.595-597

2003

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A comparison of floating-body potential in H-gate ultrathin gate oxide partially depleted SOI pMOS and nMOS devices based on 90-nm SOI CMOS process

IEEE electron device letters, 2004-04, Vol.25 (4), p.214-216

2004

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Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

IEEE transactions on electron devices, 2004-04, Vol.51 (4), p.575-580

2004

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Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

2009 IEEE International Conference on IC Design and Technology, 2009, p.21-24

2009

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Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-μm SiGe BiCMOS process

IEEE transactions on electron devices, 2003-07, Vol.50 (7), p.1683-1689

2003

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High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

2008 IEEE International Reliability Physics Symposium, 2008, p.627-628

2008

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Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007, p.594-595

2007

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Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process

IEEE electron device letters, 2003-03, Vol.24 (3), p.168-170, Article 168

2003

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Latch-up free ESD protection design with SCR structure in advanced CMOS technology

2011 International Reliability Physics Symposium, 2011, p.4C.3.1-4C.3.4

2011

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Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process

2011 International Reliability Physics Symposium, 2011, p.4C.1.1-4C.1.4

2011

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The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

2011 International Reliability Physics Symposium, 2011, p.EL.1.1-EL.1.3

2011

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Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2017, p.1-3

2017

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ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

2006 IEEE International Integrated Reliability Workshop Final Report, 2006, p.167-170

2006

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Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application

Solid state electronics letters, 2019-01, Vol.1 (1), p.25-29

2019

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Reliability investigations on a unique direct-tunneling-induced high performance partially-depleted SOI PMOS device

2004 IEEE International Reliability Physics Symposium. Proceedings, 2004, p.679-680

2004

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The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2007, p.249-252

2007

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ESD protection design with lateral DMOS transistor in 40-V BCD technology

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2010, p.1-4

2010

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Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-[mu]m SiGe BiCMOS process

IEEE transactions on electron devices, 2003-07, Vol.50 (7), p.1683

2003

Volltextzugriff (PDF)

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

IEEE transactions on electron devices, 2003-07, Vol.50 (7), p.1683-1689

2003

Volltextzugriff (PDF)

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-mum SiGe BiCMOS process

IEEE transactions on electron devices, 2003-07, Vol.50 (7), p.1683-1689

2003

Volltextzugriff (PDF)

Investigation of a SiGe HBT during ESD stress in a 0.18-mum SiGe BiCMOS process

IEEE electron device letters, 2003-03, Vol.24 (3), p.168-170

2003

Volltextzugriff (PDF)

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Optimization of PESD implant design for ESD robustness of 5V drain-back N-LDMOSFET

Lower trigger voltage design for ESD protection device applied in PMIC application

ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

Using layout technique and direct-tunneling mechanism to promote DC performance of partially depleted SOI devices

Low-leakage diode string designs using triple-well technologies for RF-ESD applications

A comparison of floating-body potential in H-gate ultrathin gate oxide partially depleted SOI pMOS and nMOS devices based on 90-nm SOI CMOS process

Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-μm SiGe BiCMOS process

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process

Latch-up free ESD protection design with SCR structure in advanced CMOS technology

Design of modified ESD protection structure with low-trigger and high-holding voltage in embedded high voltage CMOS process

The modified P+ electrode layout schemes to enhance esd robustness of SCR structure for PMIC applications

Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application

Reliability investigations on a unique direct-tunneling-induced high performance partially-depleted SOI PMOS device

The Impact of N-Drift Implant on ESD Robustness of High-Voltage NMOS with Embedded SCR Structure in 40-V CMOS Process

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-[mu]m SiGe BiCMOS process

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-mum SiGe BiCMOS process

Investigation of a SiGe HBT during ESD stress in a 0.18-mum SiGe BiCMOS process

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