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Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing

Electronics letters, 2016-03, Vol.52 (6), p.464-466

2016

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Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

Electronics letters, 2016-09, Vol.52 (19), p.1618-1620

2016

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Wire crossing constrained QCA circuit design using bilayer logic decomposition

Electronics letters, 2015-10, Vol.51 (21), p.1677-1679

2015

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Design of Testable Reversible Sequential Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1201-1209

2013

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Reversible Logic-Based Concurrently Testable Latches for Molecular QCA

IEEE transactions on nanotechnology, 2010-01, Vol.9 (1), p.62-69

2010

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IEEE_Xplore

TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

2012 IEEE International Reliability Physics Symposium (IRPS), 2012, p.5F.1.1-5F.1.12

2012

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IEEE_Xplore

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures

Advances in Computer Systems Architecture, 2005, p.805-817

2005

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Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits

2009 22nd International Conference on VLSI Design, 2009, p.511-516

2009

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IEEE_Xplore

Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs

2010 23rd International Conference on VLSI Design, 2010, p.235-240

2010

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IEEE_Xplore

Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future

2012 25th International Conference on VLSI Design, 2012, p.13-15

2012

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IEEE_Xplore

Ultrafast All-Optical Reversible Peres and Feynman-Double Logic Gates with Silicon Microring Resonators

Transactions on Computational Science XXIV, 2014, Vol.8911, p.21-36

2014

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Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic

Transactions on Computational Science XXIV, 2014, Vol.8911, p.129-146

2014

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Synthesis of Reversible Circuits Based on EXORs of Products of EXORs

Transactions on Computational Science XXIV, 2014, Vol.8911, p.111-128

2014

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A new reversible design of BCD adder

2011 Design, Automation & Test in Europe, 2011, p.1-4

2011

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IEEE_Xplore

Adiabatic CMOS: Limits of Reversible Energy Recovery and First Steps for Design Automation

Transactions on Computational Science XXIV, 2014, Vol.8911, p.1-20

2014

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Transactions on Computational Science XXIV: Special Issue on Reversible Computing

2014, 2014

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Mach-Zehnder interferometer based design of all optical reversible binary adder

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.721-726

2012

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IEEE_Xplore

Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.1815-1818

2009

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IEEE_Xplore

Novel BCD adders and their reversible logic implementation for IEEE 754r format

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006, p.6 pp.

2006

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IEEE_Xplore

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate

2009 IEEE Computer Society Annual Symposium on VLSI, 2009, p.229-234

2009

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IEEE_Xplore

A new design of the reversible subtractor circuit

2011 11th IEEE International Conference on Nanotechnology, 2011, p.1430-1435

2011

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IEEE_Xplore

Novel design and reversible logic synthesis of multiplexer based full adder and multipliers

48th Midwest Symposium on Circuits and Systems, 2005, 2005, p.1593-1596 Vol. 2

2005

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IEEE_Xplore

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates

2012 IEEE Computer Society Annual Symposium on VLSI, 2012, p.207-212

2012

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IEEE_Xplore

Transactions on Computational Science XVII

2013, 2013

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Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation

2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006, Vol.2, p.438-442

2006

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IEEE_Xplore

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Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing

Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

Wire crossing constrained QCA circuit design using bilayer logic decomposition

Design of Testable Reversible Sequential Circuits

Reversible Logic-Based Concurrently Testable Latches for Molecular QCA

TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures

Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits

Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs

Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future

Ultrafast All-Optical Reversible Peres and Feynman-Double Logic Gates with Silicon Microring Resonators

Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic

Synthesis of Reversible Circuits Based on EXORs of Products of EXORs

A new reversible design of BCD adder

Adiabatic CMOS: Limits of Reversible Energy Recovery and First Steps for Design Automation

Transactions on Computational Science XXIV: Special Issue on Reversible Computing

Mach-Zehnder interferometer based design of all optical reversible binary adder

Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate

Novel BCD adders and their reversible logic implementation for IEEE 754r format

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate

A new design of the reversible subtractor circuit

Novel design and reversible logic synthesis of multiplexer based full adder and multipliers

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates

Transactions on Computational Science XVII

Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation

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