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A Versatile Approach for Adaptive Grid Mapping and Grid Flex-Graph Exploration with a Field-Programmable Gate Array-Based Robot Using Hardware Schemes

Sensors (Basel, Switzerland), 2024-05, Vol.24 (9), p.2775

2024

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Hardware Schemes for Smarter Indoor Robotics to Prevent the Backing Crash Framework Using Field Programmable Gate Array-Based Multi-Robots

Sensors (Basel, Switzerland), 2024-03, Vol.24 (6), p.1724

2024

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A Versatile Approach to Polygonal Object Avoidance in Indoor Environments with Hardware Schemes Using an FPGA-Based Multi-Robot

Sensors (Basel, Switzerland), 2023-11, Vol.23 (23), p.9480

2023

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Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs

ACM transactions on design automation of electronic systems, 2013-01, Vol.18 (1), p.1-29

2013

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Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-05, Vol.35 (5), p.792-805

2016

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Online Map-Matching of Noisy and Sparse Location Data With Hidden Markov and Route Choice Models

IEEE transactions on intelligent transportation systems, 2017-09, Vol.18 (9), p.2423-2434

2017

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Improving accuracy of HPC-based malware classification for embedded platforms using gradient descent optimization

Journal of cryptographic engineering, 2020-11, Vol.10 (4), p.289-303

2020

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Blockchain-based public auditing for big data in cloud storage

Information processing & management, 2020-11, Vol.57 (6), p.102382, Article 102382

2020

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Efficient heuristic and tabu search for hardware/software partitioning

The Journal of supercomputing, 2013-10, Vol.66 (1), p.118-134

2013

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Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays

IEEE transactions on very large scale integration (VLSI) systems, 2010-02, Vol.18 (2), p.315-319

2010

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Hierarchical Additive Hough Transform for Lane Detection

IEEE embedded systems letters, 2010-06, Vol.2 (2), p.23-26

2010

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IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance

International Journal of Reconfigurable Computing, 2014, Vol.2014 (2014), p.1-17

2014

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Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

International Journal of Reconfigurable Computing, 2014-01, Vol.2014 (2014), p.1-14

2014

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Perceptual Full-Reference Quality Assessment of Stereoscopic Images by Considering Binocular Visual Characteristics

IEEE transactions on image processing, 2013-05, Vol.22 (5), p.1940-1953

2013

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Genetic Algorithm based EV Scheduling for On-Demand Public Transit System

Computational Science – ICCS 2019, p.595-603

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Rapid and Robust Background Modeling Technique for Low-Cost Road Traffic Surveillance Systems

IEEE transactions on intelligent transportation systems, 2020-05, Vol.21 (5), p.2204-2215

2020

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Vision-based patient monitoring: a comprehensive review of algorithms and technologies

Journal of ambient intelligence and humanized computing, 2018-04, Vol.9 (2), p.225-251

2018

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Reconfiguration algorithms for synchronous communication on switch based degradable arrays

Parallel computing, 2022-07, Vol.111, p.102901, Article 102901

2022

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Size-restricted cluster formation and cluster maintenance technique for mobile ad hoc networks

International journal of network management, 2007-03, Vol.17 (2), p.171-194

2007

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Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors

IEEE transactions on computers, 2021-07, Vol.70 (7), p.1106-1119

2021

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Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-12, Vol.40 (12), p.2508-2521

2021

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Fast Computation of Clustered Many-to-many Shortest Paths and Its Application to Map Matching

ACM transactions on spatial algorithms and systems, 2019-09, Vol.5 (3), p.1-20

2019

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Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

ACM transactions on design automation of electronic systems, 2014-11, Vol.20 (1), p.1-18

2014

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Advances in Computer Systems Architecture: 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings

1, 2005

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Rapid Techniques for Performance Estimation of Processors

Journal of research and practice in information technology, 2010-05, Vol.42 (2), p.147-165

2010

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A Versatile Approach for Adaptive Grid Mapping and Grid Flex-Graph Exploration with a Field-Programmable Gate Array-Based Robot Using Hardware Schemes

Hardware Schemes for Smarter Indoor Robotics to Prevent the Backing Crash Framework Using Field Programmable Gate Array-Based Multi-Robots

A Versatile Approach to Polygonal Object Avoidance in Indoor Environments with Hardware Schemes Using an FPGA-Based Multi-Robot

Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs

Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique

Online Map-Matching of Noisy and Sparse Location Data With Hidden Markov and Route Choice Models

Improving accuracy of HPC-based malware classification for embedded platforms using gradient descent optimization

Blockchain-based public auditing for big data in cloud storage

Efficient heuristic and tabu search for hardware/software partitioning

Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays

Hierarchical Additive Hough Transform for Lane Detection

IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance

Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

Perceptual Full-Reference Quality Assessment of Stereoscopic Images by Considering Binocular Visual Characteristics

Genetic Algorithm based EV Scheduling for On-Demand Public Transit System

Rapid and Robust Background Modeling Technique for Low-Cost Road Traffic Surveillance Systems

Vision-based patient monitoring: a comprehensive review of algorithms and technologies

Reconfiguration algorithms for synchronous communication on switch based degradable arrays

Size-restricted cluster formation and cluster maintenance technique for mobile ad hoc networks

Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors

Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs

Fast Computation of Clustered Many-to-many Shortest Paths and Its Application to Map Matching

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

Advances in Computer Systems Architecture: 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings

Rapid Techniques for Performance Estimation of Processors

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