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Photoresist coating and patterning for through-silicon via technology

Journal of micromechanics and microengineering, 2008-12, Vol.18 (12), p.125008-125008 (9)

2008

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Backside thinned CMOS imagers with high broadband quantum efficiency realised using new integration process

Electronics letters, 2008-01, Vol.44 (1), p.50-52

2008

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Diamond nanoprobes for electrical probing of nanoelectronics device structures

Microelectronic engineering, 2014-06, Vol.121, p.19-23

2014

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A low-cost uncooled infrared microbolometer detector in standard CMOS technology

IEEE transactions on electron devices, 2003-02, Vol.50 (2), p.494-502

2003

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TiN scanning probes for electrical profiling of nanoelectronics device structures

Microelectronic engineering, 2012-09, Vol.97, p.255-258

2012

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First Demonstration of Hybrid CMOS Imagers With Simultaneous Very Low Crosstalk and High-Broadband Quantum Efficiency

IEEE transactions on electron devices, 2012-10, Vol.59 (10), p.2723-2726

2012

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3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

IEEE transactions on components, packaging, and manufacturing technology (2011), 2011-06, Vol.1 (6), p.833-840

2011

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On the Fabrication of Backside Illuminated Image Sensors: Bonding Oxide, Edge Trimming and CMP Rework Routes

ECS transactions, 2015-04, Vol.64 (40), p.123-129

2015

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Diamond nanoprobes for electrical probing of nanoelectronics device structures: Nano Fabrication 2013

Microelectronic engineering, 2014, Vol.121, p.19-23

2014

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Edgeless silicon sensors for Medipix-based large-area X-ray imaging detectors

Journal of instrumentation, 2011-01, Vol.6 (1), p.C01035-C01035

2011

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A novel concept for ultra-low capacitance via-last TSV

2010 IEEE International 3D Systems Integration Conference (3DIC), 2010, p.1-4

2010

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Backside thinned CMOS imagers with high broadband quantum efficiency realised using new integration process

Electronics letters, 2008-01, Vol.44 (1), p.1-1

2008

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Low-cost uncooled infrared detectors in CMOS process

Sensors and actuators. A. Physical., 2003-12, Vol.109 (1), p.102-113

2003

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Use of Polymer Liners for 3D-WLP TSVs: Process, Reliability and Cost

ECS transactions, 2010, Vol.33 (12), p.41-54

2010

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Hybrid Backside Illuminated CMOS Imager for High-End Applications

ECS transactions, 2011, Vol.35 (30), p.53-63

2011

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Low-cost uncooled infrared detectors in CMOS process

Sensors and actuators. A. Physical., 2003-12, Vol.A109 (1-2), p.102-113

2003

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Backside illuminated thinned CMOS image sensors for space imaging

2008 IEEE Sensors, 2008, p.1429-1432

2008

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Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

2010 International Electron Devices Meeting, 2010, p.2.2.1-2.2.4

2010

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High density 20μm pitch CuSn microbump process for high-end 3D applications

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.27-31

2011

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Wafer bow of substrate transfer process for GaNLED on Si 8 inch

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 2012, p.202-205

2012

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Silicon micro-pillar filter fabrication for DNA separation in Lab-on-chip system

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 2012, p.52-56

2012

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Silicon microfilter device fabrication and characterization for diverse microfluidics applications

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.1834-1838

2011

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3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

2007 9th Electronics Packaging Technology Conference, 2007, p.222-226

2007

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Wafer-level thin film vacuum packages for MEMS using nanoporous anodic alumina membranes

2011 16th International Solid-State Sensors, Actuators and Microsystems Conference, 2011, p.974-977

2011

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Metal-bonded, hermetic 0-level package for MEMS

2010 12th Electronics Packaging Technology Conference, 2010, p.1-6

2010

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Photoresist coating and patterning for through-silicon via technology

Backside thinned CMOS imagers with high broadband quantum efficiency realised using new integration process

Diamond nanoprobes for electrical probing of nanoelectronics device structures

A low-cost uncooled infrared microbolometer detector in standard CMOS technology

TiN scanning probes for electrical profiling of nanoelectronics device structures

First Demonstration of Hybrid CMOS Imagers With Simultaneous Very Low Crosstalk and High-Broadband Quantum Efficiency

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

On the Fabrication of Backside Illuminated Image Sensors: Bonding Oxide, Edge Trimming and CMP Rework Routes

Diamond nanoprobes for electrical probing of nanoelectronics device structures: Nano Fabrication 2013

Edgeless silicon sensors for Medipix-based large-area X-ray imaging detectors

A novel concept for ultra-low capacitance via-last TSV

Backside thinned CMOS imagers with high broadband quantum efficiency realised using new integration process

Low-cost uncooled infrared detectors in CMOS process

Use of Polymer Liners for 3D-WLP TSVs: Process, Reliability and Cost

Hybrid Backside Illuminated CMOS Imager for High-End Applications

Low-cost uncooled infrared detectors in CMOS process

Backside illuminated thinned CMOS image sensors for space imaging

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

High density 20μm pitch CuSn microbump process for high-end 3D applications

Wafer bow of substrate transfer process for GaNLED on Si 8 inch

Silicon micro-pillar filter fabrication for DNA separation in Lab-on-chip system

Silicon microfilter device fabrication and characterization for diverse microfluidics applications

3D Embedding and Interconnection of Ultra Thin (≪ 20 μm) Silicon Dies

Wafer-level thin film vacuum packages for MEMS using nanoporous anodic alumina membranes

Metal-bonded, hermetic 0-level package for MEMS

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