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Defects in Silicon Crystals and Their Impact on DRAM Device Characteristics

Journal of the Electrochemical Society, 2002-04, Vol.149 (4), p.G226

2002

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Shrink potential, stability and yieldability of a multilayer vertical stacked capacitor for 64/256 MDRAM

ESSDERC '91: 21st European Solid State Device Research Conference, 1991, Vol.15 (1), p.363-366

Temmler, D.

1991

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Modeling of substrate related extrinsic oxide failure distributions

2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 2002, p.393-403

2002

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Experimental verification and numerical application of the thermodynamic approach to high-frequency noise in SiGe HBTs

Solid-state electronics, 1997-03, Vol.41 (3), p.387-390

1997

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Si/SiGe HBTs for application in low power ICs

Solid-state electronics, 1996-04, Vol.39 (4), p.471-480

1996

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Modelling and simulating the selective epitaxial growth of silicon under consideration of anisotropic growth rates

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003, 2003, p.387-390

2003

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Shrink potential, stability and yieldability of a multi-layer vertical stacked capacitor for 64/256 MDRAM

Microelectronic engineering, 1991-01, Vol.15 (1-4), p.363-366

Temmler, D

1991

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Self-Alignment Techniques to enable 40nm Trench Capacitor DRAM Technologies with 3-D Array Transistor and Single-Sided Strap

2007 IEEE Symposium on VLSI Technology, 2007, p.188-189

2007

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Highly scalable sub-50nm vertical double gate trench DRAM cell

IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004, 2004, p.57-60

2004

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Low temperature ultra-scaled fully self-aligned transistor technology (LOTUS) for SiGe-HBTs

Proceedings IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1995, p.142-151

1995

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Multilayer Vertical Stacked Capacitors (mvstc) for 64mbit and 256mbit Drams

1991 Symposium on VLSI Technology, 1991, p.13-14

Temmler, D.

1991

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Thermal Generation in Depleted Si/SiGe/Si-Structures, Grown by MBE, APCVD and RTCVD and their Correlation to the Base Currents of Double Mesa HBT's with Corresponding Blanket Epitaxial Layers

ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference, 1995, p.619-622

1995

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A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

2007 IEEE International Electron Devices Meeting, 2007, p.31-34

2007

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Influence of laser polishing on surface roughness and microstructural properties of the remelted surface boundary layer of tool steel H11

Materials & design, 2020-07, Vol.192, p.108689, Article 108689

2020

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Influence of pulse duration and pulse frequency on micro-roughness for laser micro polishing (LµP) of stainless steel AISI 410

Applied surface science, 2020-04, Vol.510, p.145272, Article 145272

2020

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Experimental investigation on a new hybrid laser process for surface structuring by vapor pressure on Ti6Al4V

Journal of materials processing technology, 2020-03, Vol.277, p.116450, Article 116450

2020

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Tribological investigations of the applicability of surface functionalization for dry extrusion processes

AIP Conference Proceedings, 2017, Vol.1896 (1)

2017

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Surface structuring by laser remelting of 1.2379 (D2) for cold forging tools in automotive applications

Journal of laser applications, 2019-05, Vol.31 (2)

2019

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Microstructure and Residual Stresses of Laser Structured Surfaces

Advanced materials research, 2014, Vol.996, p.568-573

2014

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Defects in Silicon Crystals and Their Impact on DRAM Device Characteristics

Shrink potential, stability and yieldability of a multilayer vertical stacked capacitor for 64/256 MDRAM

Modeling of substrate related extrinsic oxide failure distributions

Experimental verification and numerical application of the thermodynamic approach to high-frequency noise in SiGe HBTs

Si/SiGe HBTs for application in low power ICs

Modelling and simulating the selective epitaxial growth of silicon under consideration of anisotropic growth rates

Shrink potential, stability and yieldability of a multi-layer vertical stacked capacitor for 64/256 MDRAM

Self-Alignment Techniques to enable 40nm Trench Capacitor DRAM Technologies with 3-D Array Transistor and Single-Sided Strap

Highly scalable sub-50nm vertical double gate trench DRAM cell

Low temperature ultra-scaled fully self-aligned transistor technology (LOTUS) for SiGe-HBTs

Multilayer Vertical Stacked Capacitors (mvstc) for 64mbit and 256mbit Drams

Thermal Generation in Depleted Si/SiGe/Si-Structures, Grown by MBE, APCVD and RTCVD and their Correlation to the Base Currents of Double Mesa HBT's with Corresponding Blanket Epitaxial Layers

A novel cell arrangement enabling Trench DRAM scaling to 40nm and beyond

Influence of laser polishing on surface roughness and microstructural properties of the remelted surface boundary layer of tool steel H11

Influence of pulse duration and pulse frequency on micro-roughness for laser micro polishing (LµP) of stainless steel AISI 410

Experimental investigation on a new hybrid laser process for surface structuring by vapor pressure on Ti6Al4V

Tribological investigations of the applicability of surface functionalization for dry extrusion processes

Surface structuring by laser remelting of 1.2379 (D2) for cold forging tools in automotive applications

Microstructure and Residual Stresses of Laser Structured Surfaces

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