UB Paderborn / Katalog / Suche / in CDI

Multi-Threshold Voltage FinFET Sequential Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2011-01, Vol.19 (1), p.151-156

2011

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Localized states in an ultracold atomic gas trapped in a bichromatic potential: The effect of a time-varying phase

Communications in nonlinear science & numerical simulation, 2012-09, Vol.17 (9), p.3552-3557

Tawfik, Sherif A.

2012

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Monocrystalline Antimonene Nanosheets via Physical Vapor Deposition

Advanced materials interfaces, 2020-12, Vol.7 (24), p.n/a

2020

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Low Power and High Speed Multi Threshold Voltage Interface Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2009-05, Vol.17 (5), p.638-645

2009

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Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew

IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.347-355

2010

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Plasmonic Slot Waveguides with Core Nonlinearity

Plasmonics (Norwell, Mass.), 2014-04, Vol.9 (2), p.409-413

2014

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First principles calculation of field emission from carbon nanotubes with nitrogen and boron doping

Physica. E, Low-dimensional systems & nanostructures, 2011-10, Vol.44 (1), p.111-114

2011

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First principles calculation of field emission from nanostructures using time-dependent density functional theory: A simplified approach

Physica. E, Low-dimensional systems & nanostructures, 2011-05, Vol.43 (7), p.1360-1364

2011

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Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.60-70

2008

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Corrigendum: First principles calculation of field emission from nanostructures using time-dependent density functional theory: A simplified approach

Physica. E, Low-dimensional systems & nanostructures, 2016-09, Vol.83, p.511-511

2016

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Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

International Symposium on Low Power Electronics and Design: Proceedings of the 2007 international symposium on Low power electronics and design; 27-29 Aug. 2007, 2007, p.62-67

2007

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Low power and robust 7T dual-Vt SRAM circuit

2008 IEEE International Symposium on Circuits and Systems, 2008, p.1452-1455

2008

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Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs : Device technologies and circuit techniques for power management

IEEE transactions on electron devices, 2008, Vol.55 (1), p.60-70

2008

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Leakage-Aware Design of Nanometer SoC

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.3231-3234

2007

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Multi-Vth Level Conversion Circuits for Multi-VDD Systems

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.1397-1400

2007

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FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.431-434

2009

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Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits

2008 IEEE International Symposium on Circuits and Systems, 2008, p.788-791

2008

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FinFET domino logic with independent gate keepers

Microelectronics, 2009-11, Vol.40 (11), p.1531-1540

2009

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Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.645-648

2007

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Dynamic wordline voltage swing for low leakage and stable static memory banks

2008 IEEE International Symposium on Circuits and Systems, 2008, p.1894-1897

2008

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Manufacturable low-power latches for standard tied-double-gate FinFET technologies

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.471-474

2009

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Algorithmic truncation of minimax polynomial coefficients

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.-2424

2006

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Independent-Gate and Tied-Gate FinFET SRAM Circuits: Design Guidelines for Reduced Area and Enhanced Stability

2007 Internatonal Conference on Microelectronics, 2007, p.171-174

2007

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Portfolio of FinFET memories: Innovative techniques for an emerging technology

2008 International SoC Design Conference, 2008, Vol.1, p.I-101-I-104

2008

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High speed FinFET domino logic circuits with independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise

2007 Internatonal Conference on Microelectronics, 2007, p.175-178

2007

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Multi-Threshold Voltage FinFET Sequential Circuits

Localized states in an ultracold atomic gas trapped in a bichromatic potential: The effect of a time-varying phase

Monocrystalline Antimonene Nanosheets via Physical Vapor Deposition

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew

Plasmonic Slot Waveguides with Core Nonlinearity

First principles calculation of field emission from carbon nanotubes with nitrogen and boron doping

First principles calculation of field emission from nanostructures using time-dependent density functional theory: A simplified approach

Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

Corrigendum: First principles calculation of field emission from nanostructures using time-dependent density functional theory: A simplified approach

Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution

Low power and robust 7T dual-Vt SRAM circuit

Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs : Device technologies and circuit techniques for power management

Leakage-Aware Design of Nanometer SoC

Multi-Vth Level Conversion Circuits for Multi-VDD Systems

FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations

Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits

FinFET domino logic with independent gate keepers

Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew

Dynamic wordline voltage swing for low leakage and stable static memory banks

Manufacturable low-power latches for standard tied-double-gate FinFET technologies

Algorithmic truncation of minimax polynomial coefficients

Independent-Gate and Tied-Gate FinFET SRAM Circuits: Design Guidelines for Reduced Area and Enhanced Stability

Portfolio of FinFET memories: Innovative techniques for an emerging technology

High speed FinFET domino logic circuits with independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise

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