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Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

IEEE transactions on electron devices, 2008-01, Vol.55 (1), p.60-70

2008

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Low Power and High Speed Multi Threshold Voltage Interface Circuits

IEEE transactions on very large scale integration (VLSI) systems, 2009-05, Vol.17 (5), p.638-645

2009

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Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew

IEEE transactions on very large scale integration (VLSI) systems, 2010-03, Vol.18 (3), p.347-355

2010

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FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.431-434

2009

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EFFECT OF TILLAGE DEPTH ON SOME PROPERTIES OF SALINE SOIL

Menoufia Journal of Soil Science, 2022-09, Vol.7 (5), p.81-90

2022

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Manufacturable low-power latches for standard tied-double-gate FinFET technologies

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.471-474

2009

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Algorithmic truncation of minimax polynomial coefficients

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.-2424

2006

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Independent-Gate and Tied-Gate FinFET SRAM Circuits: Design Guidelines for Reduced Area and Enhanced Stability

2007 Internatonal Conference on Microelectronics, 2007, p.171-174

2007

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Portfolio of FinFET memories: Innovative techniques for an emerging technology

2008 International SoC Design Conference, 2008, Vol.1, p.I-101-I-104

2008

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High speed FinFET domino logic circuits with independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise

2007 Internatonal Conference on Microelectronics, 2007, p.175-178

2007

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Low-power and robust six-FinFET memory cell using selective gate-drain/source overlap engineering

Proceedings of the 2009 12th International Symposium on Integrated Circuits, 2009, p.244-247

2009

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Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation

9th International Symposium on Quality Electronic Design (isqed 2008), 2008, p.855-860

2008

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Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.443-446

2007

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Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations

9th International Symposium on Quality Electronic Design (isqed 2008), 2008, p.311-316

2008

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Parameter space exploration for robust and high-performance n-channel and p-channel symmetric double-gate FinFETs

2009 1st Asia Symposium on Quality Electronic Design, 2009, p.246-251

2009

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Mutual exploration of FinFET technology and circuit design options for implementing compact brute-force latches

2009 1st Asia Symposium on Quality Electronic Design, 2009, p.1-8

2009

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Dual-VDD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew

8th International Symposium on Quality Electronic Design (ISQED'07), 2007, p.73-78

2007

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Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.348-351

2008

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Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007, p.845-848

2007

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Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.1720-1723

2008

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Stability enhancement techniques for nanoscale SRAM circuits: A comparison

2008 International SoC Design Conference, 2008, Vol.1, p.I-113-I-116

2008

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Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations

9th International Symposium on Quality Electronic Design (isqed 2008), 2008, p.305-310

2008

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Efficient Partial Discharge Detection by Plasmonic Photonic Crystal Fiber Sensor With Bimetallic Grating

IEEE transactions on dielectrics and electrical insulation, 2022-04, Vol.29 (2), p.478-484

2022

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Plasmonic photonic crystal fiber sensor for optical partial discharge detection

Optical and quantum electronics, 2022-07, Vol.54 (7), Article 433

2022

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Identification and assessment of genetic diversity among Sargassum species from Egypt

Nucleus (Calcutta), 2021-08, Vol.64 (2), p.229-234

2021

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Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew

FinFET technology development guidelines for higher performance, lower power, and stronger resilience to parameter variations

EFFECT OF TILLAGE DEPTH ON SOME PROPERTIES OF SALINE SOIL

Manufacturable low-power latches for standard tied-double-gate FinFET technologies

Algorithmic truncation of minimax polynomial coefficients

Independent-Gate and Tied-Gate FinFET SRAM Circuits: Design Guidelines for Reduced Area and Enhanced Stability

Portfolio of FinFET memories: Innovative techniques for an emerging technology

High speed FinFET domino logic circuits with independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise

Low-power and robust six-FinFET memory cell using selective gate-drain/source overlap engineering

Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation

Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density

Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations

Parameter space exploration for robust and high-performance n-channel and p-channel symmetric double-gate FinFETs

Mutual exploration of FinFET technology and circuit design options for implementing compact brute-force latches

Dual-VDD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew

Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption

Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption

Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic

Stability enhancement techniques for nanoscale SRAM circuits: A comparison

Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations

Efficient Partial Discharge Detection by Plasmonic Photonic Crystal Fiber Sensor With Bimetallic Grating

Plasmonic photonic crystal fiber sensor for optical partial discharge detection

Identification and assessment of genetic diversity among Sargassum species from Egypt

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