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A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration

IEEE journal of solid-state circuits, 2017-10, Vol.52 (10), p.2563-2575

2017

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Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters

IEEE transactions on circuits and systems. I, Regular papers, 2019-04, Vol.66 (4), p.1342-1354

2019

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Challenges and opportunities toward fully automated analog layout design

Journal of semiconductors, 2020-11, Vol.41 (11), p.111407-84

2020

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Combination of irinotecan silicasome nanoparticles with radiation therapy sensitizes immunotherapy by modulating the activation of the cGAS/STING pathway for colorectal cancer

Materials today bio, 2023-12, Vol.23, p.100809-100809, Article 100809

2023

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A 0.7-V 0.6- \mu \text 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction

IEEE journal of solid-state circuits, 2017-05, Vol.52 (5), p.1388-1398

2017

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A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, p.1-4

2017

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27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.369-371

2021

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Error suppression techniques for energy-efficient high-resolution SAR ADCs

Journal of semiconductors, 2020-11, Vol.41 (11), p.111403-42

2020

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Design Techniques for Energy-Efficient Analog-to-Digital Converters

IEEE open journal of solid-state circuits, 2023, Vol.3, p.145-161

2023

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A 3.7-mW 12.5-MHz 81-dB SNDR 4th-Order Continuous-Time DSM With Single-OTA and 2nd-Order Noise-Shaping SAR

IEEE open journal of solid-state circuits, 2022, Vol.2, p.122-134

2022

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An In-Memory-Computing Charge-Domain Ternary CNN Classifier

2021 IEEE Custom Integrated Circuits Conference (CICC), 2021, p.1-2

2021

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A pipelined SAR ADC reusing the comparator as residue amplifier

2017 IEEE Custom Integrated Circuits Conference (CICC), 2017, p.1-4

2017

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An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier

IEEE open journal of solid-state circuits, 2021, Vol.1, p.149-161

2021

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A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp

IEEE journal of solid-state circuits, 2024-07, Vol.59 (7), p.2209-2218

2024

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A 0.004-mm 2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp

IEEE journal of solid-state circuits, 2024-07, Vol.59 (7), p.2209-2218

2024

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18.2 A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.296-297

2019

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A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-4

2015

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An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.1011-1022

2020

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A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation

IEEE journal of solid-state circuits, 2021-12, Vol.56 (12), p.3668-3680

2021

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Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

IEEE transactions on circuits and systems. I, Regular papers, 2022-06, Vol.69 (6), p.2249-2262

2022

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A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration

IEEE transactions on circuits and systems. I, Regular papers, 2019-08, Vol.66 (8), p.2876-2887

2019

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A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro

IEEE transactions on circuits and systems. I, Regular papers, 2023-05, Vol.70 (5), p.1-11

2023

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A 13-bit 0.005-mm 2 40-MS/s SAR ADC With kT/C Noise Cancellation

IEEE journal of solid-state circuits, 2020-12, Vol.55 (12), p.3260-3270

2020

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A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation

IEEE journal of solid-state circuits, 2020-12, Vol.55 (12), p.3260-3270

2020

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TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

IEEE transactions on circuits and systems. I, Regular papers, 2021-08, Vol.68 (8), p.3377-3387

2021

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A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters

Challenges and opportunities toward fully automated analog layout design

Combination of irinotecan silicasome nanoparticles with radiation therapy sensitizes immunotherapy by modulating the activation of the cGAS/STING pathway for colorectal cancer

A 0.7-V 0.6- \mu \text 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction

A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOS

27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering

Error suppression techniques for energy-efficient high-resolution SAR ADCs

Design Techniques for Energy-Efficient Analog-to-Digital Converters

A 3.7-mW 12.5-MHz 81-dB SNDR 4th-Order Continuous-Time DSM With Single-OTA and 2nd-Order Noise-Shaping SAR

An In-Memory-Computing Charge-Domain Ternary CNN Classifier

A pipelined SAR ADC reusing the comparator as residue amplifier

An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier

A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp

A 0.004-mm 2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp

18.2 A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction

An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier

A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration

A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro

A 13-bit 0.005-mm 2 40-MS/s SAR ADC With kT/C Noise Cancellation

A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks

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