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Cross point assignment with global rerouting for general-architecture designs

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-03, Vol.14 (3), p.337-348

1995

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A subsystem-oriented performance analysis methodology for shared-bus multiprocessors

IEEE transactions on parallel and distributed systems, 1996-07, Vol.7 (7), p.755-767

1996

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A new scheme for rectifying recognition results of printed chinese characters

Pattern recognition, 2001-11, Vol.34 (11), p.2121-2132

2001

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A new approach of multi-stage fuzzy logic inference

Fuzzy sets and systems, 1996, Vol.78 (1), p.51-72

1996

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Performance analysis of a separate address/data bus multiprocessor system

Journal of the Chinese Institute of Engineers, 1995-06, Vol.18 (4), p.553-563

1995

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Performance Modeling and Evaluation of a Two-Dimensional Disk Array System

Journal of parallel and distributed computing, 1996-10, Vol.38 (1), p.16-27

1996

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A polynomial-time heuristic approach to solving the false path problem

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 1996-05, Vol.43 (5), p.386-396

1996

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Doubly pipelined CORDIC array for digital signal processing algorithms

Journal of the Chinese Institute of Engineers, 1987-06, Vol.10 (4), p.375-383

1987

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High performance VLSI CORDIC algorithms, architecture and chip design

Journal of the Chinese Institute of Engineers, 1987-07, Vol.10 (5), p.493-502

1987

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A control-flow based design of automated design synthesis system

Journal of the Chinese Institute of Engineers, 1988-06, Vol.11 (4), p.349-359

1988

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Timed Boolean calculus and its applications in timing analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 1994-03, Vol.13 (3), p.318-337

1994

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Intelligent stock trading system with price trend prediction and reversal recognition using dual-module neural networks

Applied intelligence (Dordrecht, Netherlands), 1993-09, Vol.3 (3), p.225-248

1993

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Toward fast reasoning for fuzzy logic inference

International Joint Conference on Neural Networks, Nagoya, 1993, 1993, Vol.1, p.697-700 vol.1

1993

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MARS: a RISC-based architecture for Lisp

Engineering applications of artificial intelligence, 1990, Vol.3 (1), p.19-29

1990

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VLSI architecture design and implementation for TWOFISH block cipher

2002 IEEE International Symposium on Circuits and Systems (ISCAS), 2002, Vol.2, p.II-II

2002

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ASG: Automatic schematic generator

Integration (Amsterdam), 1991-03, Vol.11 (1), p.11-27

1991

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On testing wave pipelined circuits

Annual ACM IEEE Design Automation Conference: Proceedings of the 31st annual conference on Design automation; 06-10 June 1994, 1994, p.370-374

1994

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A memory management unit and cache controller for the MARS system

[1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture, 1990, p.200-208

1990

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Using timed Boolean algebra to solve false path problem in timing analysis

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, 1991, p.172-176

1991

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A new approach to solving false path problem in timing analysis

Computer-Aided Design: International Conference on (ICCAD '91), 1992

1992

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A database management system for a VLSI design system

Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988, p.257-262

1988

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MARS performance evaluation with different interconnection networks

Systems Integration '90. Proceedings of the First International Conference on Systems Integration, 1990, p.248-257

1990

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MARS-a RISC-based architecture for LISP

[Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence, 1989, p.198-206

1989

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On Testing Wave Pipelined Circuits

31st Design Automation Conference, 1994, p.370-374

1994

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ASG : automatic schemantic generator

Integration (Amsterdam), 1991, Vol.11 (1), p.11-27

1991

Volltextzugriff (PDF)

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Cross point assignment with global rerouting for general-architecture designs

A subsystem-oriented performance analysis methodology for shared-bus multiprocessors

A new scheme for rectifying recognition results of printed chinese characters

A new approach of multi-stage fuzzy logic inference

Performance analysis of a separate address/data bus multiprocessor system

Performance Modeling and Evaluation of a Two-Dimensional Disk Array System

A polynomial-time heuristic approach to solving the false path problem

Doubly pipelined CORDIC array for digital signal processing algorithms

High performance VLSI CORDIC algorithms, architecture and chip design

A control-flow based design of automated design synthesis system

Timed Boolean calculus and its applications in timing analysis

Intelligent stock trading system with price trend prediction and reversal recognition using dual-module neural networks

Toward fast reasoning for fuzzy logic inference

MARS: a RISC-based architecture for Lisp

VLSI architecture design and implementation for TWOFISH block cipher

ASG: Automatic schematic generator

On testing wave pipelined circuits

A memory management unit and cache controller for the MARS system

Using timed Boolean algebra to solve false path problem in timing analysis

A new approach to solving false path problem in timing analysis

A database management system for a VLSI design system

MARS performance evaluation with different interconnection networks

MARS-a RISC-based architecture for LISP

On Testing Wave Pipelined Circuits

ASG : automatic schemantic generator

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