UB Paderborn / Katalog / Suche / in CDI

Application-Dependent Testing of FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2006-09, Vol.14 (9), p.1024-1033

Tahoori, M.

2006

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Using Boolean satisfiability for computing soft error rates in early design stages

Microelectronics and reliability, 2010, Vol.50 (1), p.149-159

2010

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Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-12, Vol.24 (12), p.1881-1893

2005

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Testing of quantum cellular automata

IEEE transactions on nanotechnology, 2004-12, Vol.3 (4), p.432-442

2004

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Association of programmed cell death-1 (PDCD-1) gene polymorphisms with rheumatoid arthritis in Iranian patients

Clinical and experimental rheumatology, 2011-09, Vol.29 (5), p.763

2011

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Elevated levels of IL-2 and IL-21 produced by CD4+ T cells in inflammatory bowel disease

Journal of biological regulators and homeostatic agents, 2017-04, Vol.31 (2), p.279-287

2017

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Application-independent testing of FPGA interconnects

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-11, Vol.24 (11), p.1774-1783

2005

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ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), 2012, p.1-12

2012

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High Resolution Application Specific Fault Diagnosis of FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2011-10, Vol.19 (10), p.1775-1786

Tahoori, M. B.

2011

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Obtaining FPGA soft error rate in high performance information systems

Microelectronics and reliability, 2009-05, Vol.49 (5), p.551-557

2009

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On the evaluation of scaling of QCA devices in the presence of defects at manufacturing

IEEE transactions on nanotechnology, 2005-11, Vol.4 (6), p.740-743

2005

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Fault tolerance of switch blocks and switch block arrays in FPGA

IEEE transactions on very large scale integration (VLSI) systems, 2005-07, Vol.13 (7), p.794-807

2005

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Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-01, Vol.32 (1), p.100-110

2013

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Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2714-2726

2007

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A failure analysis framework of ReRAM In-Memory Logic operations

2022 IEEE International Test Conference in Asia (ITC-Asia), 2022, p.67-72

2022

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Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

IEEE transactions on very large scale integration (VLSI) systems, 2007-12, Vol.15 (12), p.1320-1331

2007

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Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

2018 IEEE International Test Conference (ITC), 2018, p.1-10

2018

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Machine learning based soft error rate estimation of pass transistor logic in high-speed communication

2022 IEEE European Test Symposium (ETS), 2022, p.1-4

2022

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Polymorphism of Foxp3 gene affects the frequency of regulatory T cells and disease activity in patients with rheumatoid arthritis in Iranian population

Immunology letters, 2018-12, Vol.204, p.16-22

2018

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Variation and defect tolerance for diode-based nano crossbars

Nano communication networks, 2010-12, Vol.1 (4), p.264-272

Tahoori, M.B.

2010

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Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications

2018 IEEE International Test Conference (ITC), 2018, p.1-10

2018

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A universal spintronic technology based on multifunctional standardized stack

Proceedings of the 23rd Conference on Design, Automation and Test in Europe, 2020, p.394-399

2020

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NBTI mitigation by optimized NOP assignment and insertion

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.218-223

2012

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Automatic configuration generation for FPGA interconnect testing

Proceedings. 21st VLSI Test Symposium, 2003, 2003, p.134-139

2003

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A Universal Spintronic Technology based on Multifunctional Standardized Stack

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.394-399

2020

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Application-Dependent Testing of FPGAs

Using Boolean satisfiability for computing soft error rates in early design stages

Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation

Testing of quantum cellular automata

Association of programmed cell death-1 (PDCD-1) gene polymorphisms with rheumatoid arthritis in Iranian patients

Elevated levels of IL-2 and IL-21 produced by CD4+ T cells in inflammatory bowel disease

Application-independent testing of FPGA interconnects

ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level

High Resolution Application Specific Fault Diagnosis of FPGAs

Obtaining FPGA soft error rate in high performance information systems

On the evaluation of scaling of QCA devices in the presence of defects at manufacturing

Fault tolerance of switch blocks and switch block arrays in FPGA

Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

A failure analysis framework of ReRAM In-Memory Logic operations

Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication

Polymorphism of Foxp3 gene affects the frequency of regulatory T cells and disease activity in patients with rheumatoid arthritis in Iranian population

Variation and defect tolerance for diode-based nano crossbars

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications

A universal spintronic technology based on multifunctional standardized stack

NBTI mitigation by optimized NOP assignment and insertion

Automatic configuration generation for FPGA interconnect testing

A Universal Spintronic Technology based on Multifunctional Standardized Stack

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