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Using Boolean satisfiability for computing soft error rates in early design stages

Microelectronics and reliability, 2010, Vol.50 (1), p.149-159

2010

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Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-12, Vol.24 (12), p.1881-1893

2005

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Testing of quantum cellular automata

IEEE transactions on nanotechnology, 2004-12, Vol.3 (4), p.432-442

2004

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Application-independent testing of FPGA interconnects

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-11, Vol.24 (11), p.1774-1783

2005

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ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012), 2012, p.1-12

2012

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On the evaluation of scaling of QCA devices in the presence of defects at manufacturing

IEEE transactions on nanotechnology, 2005-11, Vol.4 (6), p.740-743

2005

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Obtaining FPGA soft error rate in high performance information systems

Microelectronics and reliability, 2009-05, Vol.49 (5), p.551-557

2009

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High Resolution Application Specific Fault Diagnosis of FPGAs

IEEE transactions on very large scale integration (VLSI) systems, 2011-10, Vol.19 (10), p.1775-1786

Tahoori, M. B.

2011

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Fault tolerance of switch blocks and switch block arrays in FPGA

IEEE transactions on very large scale integration (VLSI) systems, 2005-07, Vol.13 (7), p.794-807

2005

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Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-01, Vol.32 (1), p.100-110

2013

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Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

2018 IEEE International Test Conference (ITC), 2018, p.1-10

2018

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Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2714-2726

2007

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Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

IEEE transactions on very large scale integration (VLSI) systems, 2007-12, Vol.15 (12), p.1320-1331

2007

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Variation-aware Fault Modeling and Test Generation for STT-MRAM

2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2019, p.80-83

2019

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Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications

2018 IEEE International Test Conference (ITC), 2018, p.1-10

2018

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Variation and defect tolerance for diode-based nano crossbars

Nano communication networks, 2010-12, Vol.1 (4), p.264-272

Tahoori, M.B.

2010

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Automatic configuration generation for FPGA interconnect testing

Proceedings. 21st VLSI Test Symposium, 2003, 2003, p.134-139

2003

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NBTI mitigation by optimized NOP assignment and insertion

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.218-223

2012

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A cross-layer approach for resiliency and energy efficiency in Near Threshold Computing

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, p.1-8

2016

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Ping-pong test: Compact test vector generation for reversible circuits

2012 IEEE 30th VLSI Test Symposium (VTS), 2012, p.164-169

2012

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Online Missing/Repeated Gate Faults Detection in Reversible Circuits

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011, p.435-442

2011

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Statistical analysis of BTI in the presence of process-induced voltage and temperature variations

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, p.594-600

2013

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Chip-level modeling and analysis of electrical masking of soft errors

2013 IEEE 31st VLSI Test Symposium (VTS), 2013, p.1-6

2013

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Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, p.1609-1614

2012

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Techniques and algorithms for fault grading of FPGA interconnect test configurations

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-02, Vol.23 (2), p.261-272

2004

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Using Boolean satisfiability for computing soft error rates in early design stages

Characterization, test, and logic synthesis of and-or-inverter (AOI) gate design for QCA implementation

Testing of quantum cellular automata

Application-independent testing of FPGA interconnects

ExtraTime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level

On the evaluation of scaling of QCA devices in the presence of defects at manufacturing

Obtaining FPGA soft error rate in high performance information systems

High Resolution Application Specific Fault Diagnosis of FPGAs

Fault tolerance of switch blocks and switch block arrays in FPGA

Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM

Soft Error Susceptibility Analysis of SRAM-Based FPGAs in High-Performance Information Systems

Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

Variation-aware Fault Modeling and Test Generation for STT-MRAM

Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications

Variation and defect tolerance for diode-based nano crossbars

Automatic configuration generation for FPGA interconnect testing

NBTI mitigation by optimized NOP assignment and insertion

A cross-layer approach for resiliency and energy efficiency in Near Threshold Computing

Ping-pong test: Compact test vector generation for reversible circuits

Online Missing/Repeated Gate Faults Detection in Reversible Circuits

Statistical analysis of BTI in the presence of process-induced voltage and temperature variations

Chip-level modeling and analysis of electrical masking of soft errors

Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells

Techniques and algorithms for fault grading of FPGA interconnect test configurations

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