UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Effects of Low- k Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Japanese Journal of Applied Physics, 2012-09, Vol.51 (9R), p.96504

2012

Volltextzugriff (PDF)

Moisture Uptake Impact on Damage Layer of Porous Low-k Film in 80nm-Pitched Cu Interconnects

ECS transactions, 2011, Vol.41 (7), p.405-413

2011

Volltextzugriff (PDF)

Effects of Low-$k$ Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Japanese Journal of Applied Physics, 2012-09, Vol.51 (9), p.096504-096504-9

2012

Volltextzugriff (PDF)

CMOS Directly Bonded to Array (CBA) Technology for Future 3D Flash Memory

2023 International Electron Devices Meeting (IEDM), 2023, p.1-4

Tagami, Masayoshi

2023

Volltextzugriff (PDF)

Thermal Stress Control in Cu Dual Damascene Interconnects with Low-k Organic Polymer Film

Journal of the Electrochemical Society, 2010, Vol.157 (12), p.H1071

2010

Volltextzugriff (PDF)

Mechanical Property Control of Low-k Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects

Japanese Journal of Applied Physics, 2004-04, Vol.43 (4S), p.1807

2004

Volltextzugriff (PDF)

Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low- k / rm Cu Interconnects

IEEE transactions on components, packaging, and manufacturing technology (2011), 2013-03, Vol.3 (3), p.384-390

2013

Volltextzugriff (PDF)

Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low-[Formula Omitted] Interconnects

IEEE transactions on components, packaging, and manufacturing technology (2011), 2013-03, Vol.3 (3), p.384

2013

Volltextzugriff (PDF)

Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low- k/ Interconnects

IEEE transactions on components, packaging, and manufacturing technology (2011), 2013-03, Vol.3 (3), p.384-390

2013

Volltextzugriff (PDF)

Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles

IEEE transactions on electron devices, 2009-08, Vol.56 (8), p.1579-1587

2009

Volltextzugriff (PDF)

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

IEEE transactions on semiconductor manufacturing, 2008-08, Vol.21 (3), p.469-480

2008

Volltextzugriff (PDF)

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

IEEE transactions on electron devices, 2006-05, Vol.53 (5), p.1169-1179

2006

Volltextzugriff (PDF)

Robust Ultrathin (20-25 nm)Trilayer Dielectric Low k Cu Damascene Cap for Sub-30 nm Nanoelectric Devices

ECS transactions, 2012-05, Vol.41 (43), p.3-9

2012

Volltextzugriff (PDF)

Porous Low-k Impacts on Performance of Advanced LSI Devices with GHz Operations

Japanese Journal of Applied Physics, 2009-04, Vol.48 (4S), p.4

2009

Volltextzugriff (PDF)

Improvement of Line-to-line TDDB by Cu and Barrier-metal Recess Structure for high voltage circuit in 3D Flash Memory

2022 IEEE International Interconnect Technology Conference (IITC), 2022, p.45-47

2022

Volltextzugriff (PDF)

Via-Shape-Control for Copper Dual-Damascene Interconnects With Low-k Organic Film

IEEE transactions on semiconductor manufacturing, 2008-05, Vol.21 (2), p.256-262

2008

Volltextzugriff (PDF)

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

IEEE transactions on semiconductor manufacturing, 2006-11, Vol.19 (4), p.455-464

2006

Volltextzugriff (PDF)

Evaluation of CVD/PVD multilayered seed for electrochemical deposition of Cu-damascene interconnects

IEEE transactions on electron devices, 2002-05, Vol.49 (5), p.733-738

2002

Volltextzugriff (PDF)

Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation

IEICE transactions on electronics, 2007-04, Vol.E90-C (4), p.848-855

2007

Volltextzugriff (PDF)

Moisture Uptake Impact on Damage Layer of Porous Low-k Film in 80nm-Pitched Cu Interconnects

Meeting abstracts (Electrochemical Society), 2011-08, Vol.MA2011-02 (32), p.2138-2138

2011

Volltextzugriff (PDF)

Robust Ultrathin (20-25 nm)Trilayer Dielectric Low k Cu Damascene Cap for Sub-30 nm Nanoelectric Devices

Meeting abstracts (Electrochemical Society), 2011-08, Vol.MA2011-02 (28), p.1933-1933

2011

Volltextzugriff (PDF)

A Robust Low-[Formula Omitted]/Cu Dual Damascene Interconnect (DDI) With Sidewall Protection Layer (SPL)

IEEE transactions on device and materials reliability, 2011-03, Vol.11 (1), p.98

2011

Volltextzugriff (PDF)

A Robust Low- k/Cu Dual Damascene Interconnect (DDI) With Sidewall Protection Layer (SPL)

IEEE transactions on device and materials reliability, 2011-03, Vol.11 (1), p.98-105

2011

Volltextzugriff (PDF)

Nanopore sequencing reveals TACC2 locus complexity and diversity of isoforms transcribed from an intronic promoter

Scientific reports, 2021-04, Vol.11 (1), p.9355-9355, Article 9355

2021

Volltextzugriff (PDF)

Publisher Correction: Nanopore sequencing reveals TACC2 locus complexity and diversity of isoforms transcribed from an intronic promoter

Scientific reports, 2021-08, Vol.11 (1), p.16835-16835, Article 16835

2021

Volltextzugriff (PDF)

1 – 25 von 43

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(34)
Mit Volltextzugriff
(30)

Publikationsform

Sprache

Englisch
(43)
Japanisch
(1)

Erscheinungsjahr

n.n

Menü

Weitere Dienste

Einstellungen

Effects of Low- k Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

Moisture Uptake Impact on Damage Layer of Porous Low-k Film in 80nm-Pitched Cu Interconnects

Effects of Low-$k$ Stack Structure on Performance of Complementary Metal Oxide Semiconductor Devices and Chip Package Interaction Failure

CMOS Directly Bonded to Array (CBA) Technology for Future 3D Flash Memory

Thermal Stress Control in Cu Dual Damascene Interconnects with Low-k Organic Polymer Film

Mechanical Property Control of Low-k Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects

Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low- k / rm Cu Interconnects

Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low-[Formula Omitted] Interconnects

Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low- k/ Interconnects

Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust Ultrathin (20-25 nm)Trilayer Dielectric Low k Cu Damascene Cap for Sub-30 nm Nanoelectric Devices

Porous Low-k Impacts on Performance of Advanced LSI Devices with GHz Operations

Improvement of Line-to-line TDDB by Cu and Barrier-metal Recess Structure for high voltage circuit in 3D Flash Memory

Via-Shape-Control for Copper Dual-Damascene Interconnects With Low-k Organic Film

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Evaluation of CVD/PVD multilayered seed for electrochemical deposition of Cu-damascene interconnects

Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation

Moisture Uptake Impact on Damage Layer of Porous Low-k Film in 80nm-Pitched Cu Interconnects

Robust Ultrathin (20-25 nm)Trilayer Dielectric Low k Cu Damascene Cap for Sub-30 nm Nanoelectric Devices

A Robust Low-[Formula Omitted]/Cu Dual Damascene Interconnect (DDI) With Sidewall Protection Layer (SPL)

A Robust Low- k/Cu Dual Damascene Interconnect (DDI) With Sidewall Protection Layer (SPL)

Nanopore sequencing reveals TACC2 locus complexity and diversity of isoforms transcribed from an intronic promoter

Publisher Correction: Nanopore sequencing reveals TACC2 locus complexity and diversity of isoforms transcribed from an intronic promoter

Suchergebnisse filtern