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DC-DC Converter-Aware Power Management for Low-Power Embedded Systems

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-08, Vol.26 (8), p.1367-1381

2007

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Applications of Voltammetry in Lithium Ion Battery Research

Journal of Electrochemical Science and Technology, 2020-02, Vol.11 (1), p.14-25

2020

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Tracking the Influence of Thermal Expansion and Oxygen Vacancies on the Thermal Stability of Ni‐Rich Layered Cathode Materials

Advanced science, 2020-06, Vol.7 (12), p.1902413-n/a

2020

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Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-04, Vol.36 (4), p.641-654

2017

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Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks

Journal of computing science and engineering : JCSE, 2022-06, Vol.16 (2), p.79-87

2022

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Synthesis of TSV Fault-Tolerant 3-D Clock Trees

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-02, Vol.34 (2), p.266-279

2015

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Design and Utilization of Multi-Skewed Multi-Bit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-09, p.1-1

2024

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Facile Fabrication of α-Alumina Hollow Fiber-Supported ZIF-8 Membrane Module and Impurity Effects on Propylene Separation Performance

Membranes (Basel), 2022-10, Vol.12 (10), p.1015

2022

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A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-03, Vol.33 (3), p.423-436

2014

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Recent Research in Design and Technology Co-Optimization with Multi-Bit Flip-Flops

2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS), 2024, p.33-36

Kim, Taewhan

2024

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CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-02, Vol.43 (2), p.1-1

2024

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Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-03, Vol.41 (3), p.656-668

2022

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Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-12, Vol.35 (12), p.2068-2081

2016

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Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-11, Vol.31 (11), p.1684-1697

2012

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Circuit Timing Analysis and Optimization under Flexible Flip-flop Timing Model

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2017, 17(6), 78, pp.862-877

2017

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Statistical Viability Analysis for Detecting False Paths Under Delay Variation

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-01, Vol.32 (1), p.111-123

2013

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Pre-route timing prediction and optimization with graph neural network models

Integration (Amsterdam), 2024-11, Vol.99, p.102262, Article 102262

2024

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Placement legalization for heterogeneous cells of non-integer multiple-heights

Integration (Amsterdam), 2024-07, Vol.97, p.102177, Article 102177

2024

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Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller

IEEE transactions on very large scale integration (VLSI) systems, 2021-07, Vol.29 (7), p.1437-1450

2021

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Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-01, Vol.32 (1), p.138-151

2013

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Allocation of multi-bit flip-flops in logic synthesis for power optimization

2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016, p.1-6

2016

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Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Integration (Amsterdam), 2014-03, Vol.47 (2), p.184-194

2014

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An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-03, Vol.32 (3), p.392-405

2013

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Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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ECO routing based on network flow method

Integration (Amsterdam), 2022-09, Vol.86, p.1-8

2022

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DC-DC Converter-Aware Power Management for Low-Power Embedded Systems

Applications of Voltammetry in Lithium Ion Battery Research

Tracking the Influence of Thermal Expansion and Oxygen Vacancies on the Thermal Stability of Ni‐Rich Layered Cathode Materials

Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling

Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks

Synthesis of TSV Fault-Tolerant 3-D Clock Trees

Design and Utilization of Multi-Skewed Multi-Bit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach

Facile Fabrication of α-Alumina Hollow Fiber-Supported ZIF-8 Membrane Module and Impurity Effects on Propylene Separation Performance

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems

Recent Research in Design and Technology Co-Optimization with Multi-Bit Flip-Flops

CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement

Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling

Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis

Circuit Timing Analysis and Optimization under Flexible Flip-flop Timing Model

Statistical Viability Analysis for Detecting False Paths Under Delay Variation

Pre-route timing prediction and optimization with graph neural network models

Placement legalization for heterogeneous cells of non-integer multiple-heights

Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller

Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree

Allocation of multi-bit flip-flops in logic synthesis for power optimization

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs

Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing

ECO routing based on network flow method

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