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Single amplifier bi-quadratic filter topologies in transimpedance configuration

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.820-823 Vol. 1

2005

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Single Amplifier Bi-Quadratic Filter Topologies in Transimpedance Configuration

IEEE transactions on circuits and systems. II, Express briefs, 2008-06, Vol.55 (6), p.502-506

2008

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Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.5545-5548 Vol. 6

2005

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An improved frequency compensation techinique for low power, low voltage CMOS amplifiers [techinique read technique]

2004 IEEE International Symposium on Circuits and Systems (ISCAS), 2004, Vol.1, p.I-497

Tadeparthy, P.

2004

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An improved frequency compensation techinique for low power,low voltage cmos amplifiers

TADEPARTHY, Preetam

2004

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A CMOS bandgap reference with correction for device-to-device variation

TADEPARTHY, Preetam

2004

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Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps

2002 IEEE International Symposium on Circuits and Systems (ISCAS), 2002, Vol.5, p.V-V

2002

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A 115mW 12-bit 50 MSPS pipelined ADC

2002 IEEE International Symposium on Circuits and Systems (ISCAS), 2002, Vol.1, p.I-I

2002

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A low power 10 bit 80 MSPS pipelined ADC in digital CMOS process

The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002, 2002, Vol.1, p.I-579

2002

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Single amplifier bi-quadratic filter topologies in transimpedance configuration

Single Amplifier Bi-Quadratic Filter Topologies in Transimpedance Configuration

Automated design of a 10-bit, 80MSPS WLAN DAC for linearity and low-area

An improved frequency compensation techinique for low power, low voltage CMOS amplifiers [techinique read technique]

An improved frequency compensation techinique for low power,low voltage cmos amplifiers

A CMOS bandgap reference with correction for device-to-device variation

Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps

A 115mW 12-bit 50 MSPS pipelined ADC

A low power 10 bit 80 MSPS pipelined ADC in digital CMOS process

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