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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

IPSJ Transactions on System LSI Design Methodology, 2017, Vol.10, pp.45-62

2017

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Postgrid Clock Routing for High Performance Microprocessor Designs

IEEE transactions on computer-aided design of integrated circuits and systems, 2012-02, Vol.31 (2), p.255-259

2012

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Techniques for Fast Physical Synthesis

Proceedings of the IEEE, 2007-03, Vol.95 (3), p.573-599

2007

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Fast Algorithms for Slew-Constrained Minimum Cost Buffering

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-11, Vol.26 (11), p.2009-2022

2007

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Multilevel circuit clustering for delay minimization

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-07, Vol.23 (7), p.1073-1085

2004

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RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-12, Vol.27 (12), p.2156-2168

2008

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Accurate estimation of global buffer delay within a floorplan

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1140-1145

2006

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Porosity-aware buffered Steiner tree construction

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-04, Vol.23 (4), p.517-526

2004

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Optimal circuit clustering for delay minimization under a more general delay model

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-05, Vol.22 (5), p.646-651

2003

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Path-Based Buffer Insertion

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-07, Vol.26 (7), p.1346-1355

2007

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Path based buffer insertion

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.509-514

2005

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NTDB: Thermodynamic Database for Nucleic Acids

Nucleic acids research, 2001-01, Vol.29 (1), p.230-233

2001

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Navigating registers in placement for clock network minimization

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.176-181

2005

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Timing-driven Steiner trees are (practically) free

2006 43rd ACM/IEEE Design Automation Conference, 2006, p.389-392

2006

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Fast algorithms for slew constrained minimum cost buffering

Annual ACM IEEE Design Automation Conference: Proceedings of the 43rd annual conference on Design automation; 24-28 July 2006, 2006, p.308-313

2006

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Integrated Placement and Skew Optimization for Rotary Clocking

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.1-6

2006

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NTDB: Thermodynamic Database for Nucleic Acids, Version 2.0

Nucleic acids research, 2003-01, Vol.31 (1), p.483-485

2003

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Skew scheduling and clock routing for improved tolerance to process variations

Proceedings of the 2005 Asia and South Pacific Design Automation Conference, 2005, p.594-599

2005

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Accurate estimation of global buffer delay within a floorplan

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004, 2004, p.706-711

2004

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Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-04, Vol.34 (4), p.501-501

2015

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Challenges of cell selection algorithms in industrial high performance microprocessor designs

Integration (Amsterdam), 2016-01, Vol.52, p.347-354

2016

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Wire synthesizable global routing for timing closure

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011, p.545-550

2011

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Placement: hot or not?

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012, p.283-290

2012

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Performance-driven multi-level clustering for combinational circuits

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003, p.729-740

2003

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Gate sizing and threshold voltage assignment for high performance microprocessor designs

The 20th Asia and South Pacific Design Automation Conference, 2015, p.214-219

2015

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Postgrid Clock Routing for High Performance Microprocessor Designs

Techniques for Fast Physical Synthesis

Fast Algorithms for Slew-Constrained Minimum Cost Buffering

Multilevel circuit clustering for delay minimization

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

Accurate estimation of global buffer delay within a floorplan

Porosity-aware buffered Steiner tree construction

Optimal circuit clustering for delay minimization under a more general delay model

Path-Based Buffer Insertion

Path based buffer insertion

NTDB: Thermodynamic Database for Nucleic Acids

Navigating registers in placement for clock network minimization

Timing-driven Steiner trees are (practically) free

Fast algorithms for slew constrained minimum cost buffering

Integrated Placement and Skew Optimization for Rotary Clocking

NTDB: Thermodynamic Database for Nucleic Acids, Version 2.0

Skew scheduling and clock routing for improved tolerance to process variations

Accurate estimation of global buffer delay within a floorplan

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes

Challenges of cell selection algorithms in industrial high performance microprocessor designs

Wire synthesizable global routing for timing closure

Placement: hot or not?

Performance-driven multi-level clustering for combinational circuits

Gate sizing and threshold voltage assignment for high performance microprocessor designs

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