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Schottky barriers in carbon nanotube-metal contacts

Journal of applied physics, 2011-12, Vol.110 (11), p.111101-111101-16

2011

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III–V Nanowire Complementary Metal–Oxide Semiconductor Transistors Monolithically Integrated on Si

Nano letters, 2015-12, Vol.15 (12), p.7898-7904

2015

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Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade

Nano letters, 2017-07, Vol.17 (7), p.4373-4380

2017

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Determination of the Bending Rigidity of Graphene via Electrostatic Actuation of Buckled Membranes

Nano letters, 2012-07, Vol.12 (7), p.3526-3531

2012

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Scaling of Vertical InAs-GaSb Nanowire Tunneling Field-Effect Transistors on Si

IEEE electron device letters, 2016-05, Vol.37 (5), p.549-552

2016

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IEEE_Xplore

Vertical InAs/InGaAs Heterostructure Metal–Oxide–Semiconductor Field-Effect Transistors on Si

Nano letters, 2017-10, Vol.17 (10), p.6006-6010

2017

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Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors

Nano letters, 2013-12, Vol.13 (12), p.5919-5924

2013

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Net-zero deep decarbonization pathways in Latin America: Challenges and opportunities

Energy strategy reviews, 2020-07, Vol.30, p.100510, Article 100510

2020

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Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

IEEE journal of the Electron Devices Society, 2019, Vol.7, p.70-75

2019

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Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

IEEE transactions on electron devices, 2013-09, Vol.60 (9), p.2761-2767

2013

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IEEE_Xplore

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

IEEE electron device letters, 2016-08, Vol.37 (8), p.966-969

2016

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IEEE_Xplore

A low GHG development pathway design framework for agriculture, forestry and land use

Energy strategy reviews, 2021-09, Vol.37, p.100683, Article 100683

2021

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Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec

IEEE electron device letters, 2023-07, Vol.44 (7), p.1064

2023

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Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S

IEEE electron device letters, 2023-01, Vol.44 (7), p.1064

2023

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A Self-Aligned Gate-Last Process Applied to All-III-V CMOS on Si

IEEE electron device letters, 2018-07, Vol.39 (7), p.935-938

2018

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IEEE_Xplore

InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors

IEEE transactions on electron devices, 2017-11, Vol.64 (11), p.4746-4751

2017

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IEEE_Xplore

Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungsten

Nano letters, 2023-06, Vol.23 (11), p.4756-4761

2023

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Vertical Nanowire TFETs With Channel Diameter Down to 10 nm and Point SMIN of 35 mV/Decade

IEEE electron device letters, 2018-07, Vol.39 (7), p.1089-1091

2018

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IEEE_Xplore

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing

Nanotechnology, 2022-02, Vol.33 (7), p.75202

2022

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Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec

IEEE electron device letters, 2023-07, Vol.44 (7), p.1064-1067

2023

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IEEE_Xplore

Low-frequency Noise in Vertical InAs/InGaAs Gate-all-around MOSFETs at 15 K for Cryogenic Applications

IEEE electron device letters, 2022-12, Vol.43 (12), p.1-1

2022

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IEEE_Xplore

Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth

Nanotechnology, 2020-08, Vol.31 (32), p.325303-325303

2020

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Diameter-Dependent Photocurrent in InAsSb Nanowire Infrared Photodetectors

Nano letters, 2013-04, Vol.13 (4), p.1380-1385

2013

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Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si

IEEE transactions on electron devices, 2020-10, Vol.67 (10), p.4118-4122

2020

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IEEE_Xplore

Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors

ACS applied materials & interfaces, 2023-04, Vol.15 (15), p.19085-19091

2023

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Schottky barriers in carbon nanotube-metal contacts

III–V Nanowire Complementary Metal–Oxide Semiconductor Transistors Monolithically Integrated on Si

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade

Determination of the Bending Rigidity of Graphene via Electrostatic Actuation of Buckled Membranes

Scaling of Vertical InAs-GaSb Nanowire Tunneling Field-Effect Transistors on Si

Vertical InAs/InGaAs Heterostructure Metal–Oxide–Semiconductor Field-Effect Transistors on Si

Combining Axial and Radial Nanowire Heterostructures: Radial Esaki Diodes and Tunnel Field-Effect Transistors

Net-zero deep decarbonization pathways in Latin America: Challenges and opportunities

Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs

Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

A low GHG development pathway design framework for agriculture, forestry and land use

Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec

Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S

A Self-Aligned Gate-Last Process Applied to All-III-V CMOS on Si

InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors

Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungsten

Vertical Nanowire TFETs With Channel Diameter Down to 10 nm and Point SMIN of 35 mV/Decade

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing

Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec

Low-frequency Noise in Vertical InAs/InGaAs Gate-all-around MOSFETs at 15 K for Cryogenic Applications

Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth

Diameter-Dependent Photocurrent in InAsSb Nanowire Infrared Photodetectors

Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si

Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors

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