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A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS

IEEE journal of solid-state circuits, 2019-04, Vol.54 (4), p.992-1002

2019

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A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications

IEEE MICRO, 2024-03, Vol.44 (2), p.61-70

2024

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A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS

IEEE journal of solid-state circuits, 2021-04, Vol.56 (4), p.1082-1092

2021

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A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries

2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2023, p.58-59

2023

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Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.216-217

2022

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A 2.9-33.0 TOPS/W Reconfigurable 1-D/2-D Compute-Near-Memory Inference Accelerator in 10-nm FinFET CMOS

IEEE solid-state circuits letters, 2020, Vol.3, p.118-121

2020

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A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS

IEEE solid-state circuits letters, 2020, Vol.3, p.338-341

2020

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A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, p.220-225

2022

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System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars

2022 IEEE Custom Integrated Circuits Conference (CICC), 2022, p.01-08

2022

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11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.210-212

2024

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A synthesis methodology for application-specific logic-in-memory designs

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

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25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.396-398

2020

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Fast Smith-Waterman hardware implementation

2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010, p.1-4

2010

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Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware

2013 IEEE High Performance Extreme Computing Conference (HPEC), 2013, p.1-6

2013

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A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing

2013 IEEE International 3D Systems Integration Conference (3DIC), 2013, p.1-7

2013

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A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS

2018 IEEE Symposium on VLSI Circuits, 2018, p.255-256

2018

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A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS

A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS

A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries

Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications

A 2.9-33.0 TOPS/W Reconfigurable 1-D/2-D Compute-Near-Memory Inference Accelerator in 10-nm FinFET CMOS

A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS

A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows

System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars

11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint

A synthesis methodology for application-specific logic-in-memory designs

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

Fast Smith-Waterman hardware implementation

Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware

A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing

A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS

A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS

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