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Steep-slope hysteresis-free negative capacitance MoS2 transistors

Nature nanotechnology, 2017-12, Vol.13 (1), p.24-28

2017

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On the thickness dependence of the polarization switching kinetics in HfO2-based ferroelectric

Applied physics letters, 2022-08, Vol.121 (8)

2022

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Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH₃ Plasma and Microwave Annealing

IEEE transactions on electron devices, 2020-04, Vol.67 (4), p.1-5

2020

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Demonstration of Highly Robust 5 nm Hf0.5Zr0.5O₂ Ultra-Thin Ferroelectric Capacitor by Improving Interface Quality

IEEE electron device letters, 2021-09, Vol.42 (9), p.1299-1302

2021

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Effects of Annealing on Ferroelectric Hafnium-Zirconium-Oxide-Based Transistor Technology

IEEE electron device letters, 2019-03, Vol.40 (3), p.467-470

2019

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Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

IEEE electron device letters, 2021-08, Vol.42 (8), p.1144-1147

2021

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Innovative Recovery Strategy for MFIS-FeFETs at Optimal Timing With Robust Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02%), and Self-Tracking Circuit Design

IEEE transactions on electron devices, 2024-05, Vol.71 (5), p.3371-3376

2024

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Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

IEEE transactions on electron devices, 2020-09, Vol.67 (9), p.3504-3509

2020

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Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures

IEEE electron device letters, 2020-09, Vol.41 (9), p.1-1

2020

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Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

IEEE electron device letters, 2011-04, Vol.32 (4), p.521-523

2011

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First Demonstration of Ferroelectric Tunnel Thin-Film Transistor Nonvolatile Memory With Polycrystalline-Silicon Channel and HfZrO } Gate Dielectric

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.1-6

2022

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Impact of Nanosheet Thickness on Performance and Reliability of Polycrystalline-Silicon Thin-Film Transistors With Double-Gate Operation

IEEE transactions on nanotechnology, 2023, Vol.22, p.740-746

2023

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Monolithically Integrated Polysilicon/Oxide-Semiconductor Hybrid Thin-Film Transistors for Advanced Sensing

IEEE journal of the Electron Devices Society, 2023, Vol.11, p.490-496

2023

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Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model

IEEE journal of the Electron Devices Society, 2022, Vol.10, p.115-122

2022

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Effects of Annealing Temperature on TiN/Hf0.5Zr0.5O2/TiN Ferroelectric Capacitor Prepared by In-Situ Like Consecutive Atomic Layer Deposition

IEEE transactions on nanotechnology, 2022, Vol.21, p.328-331

2022

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Effective N-methyl-2-pyrrolidone wet cleaning for fabricating high-performance monolayer MoS2 transistors

Nano research, 2019-02, Vol.12 (2), p.303-308

2019

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Steep-slope hysteresis-free negative capacitance MoS2 transistors

Nature nanotechnology, 2018, Vol.13 (1), p.24-28

2018

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Identification of the scraping quality for the machine tool using the smartphone

International journal of advanced manufacturing technology, 2019-12, Vol.105 (7-8), p.3451-3461

2019

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Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET

NPJ 2D materials and applications, 2023-02, Vol.7 (1), p.9-8, Article 9

2023

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Enhancement of Ferroelectricity in 5 nm Metal-Ferroelectric-Insulator Technologies by Using a Strained TiN Electrode

Nanomaterials (Basel, Switzerland), 2022-01, Vol.12 (3), p.468

2022

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Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

Frontiers in nanotechnology, 2022-01, Vol.3

2022

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3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM

IEEE journal of the Electron Devices Society, 2023, Vol.11, p.107-113

2023

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DC-free Method to Evaluate Nanoscale Equivalent Oxide Thickness: Dark-Mode Scanning Capacitance Microscopy

Nanomaterials (Basel, Switzerland), 2024-05, Vol.14 (11), p.934

2024

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Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

IEEE journal of the Electron Devices Society, 2020, Vol.8, p.474-480

2020

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Trapping Depth and Transition Probability of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor

IEEE transactions on nanotechnology, 2020, Vol.19, p.338-343

2020

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Steep-slope hysteresis-free negative capacitance MoS2 transistors

On the thickness dependence of the polarization switching kinetics in HfO2-based ferroelectric

Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH₃ Plasma and Microwave Annealing

Demonstration of Highly Robust 5 nm Hf0.5Zr0.5O₂ Ultra-Thin Ferroelectric Capacitor by Improving Interface Quality

Effects of Annealing on Ferroelectric Hafnium-Zirconium-Oxide-Based Transistor Technology

Robust Binary Neural Network Operation From 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses

Innovative Recovery Strategy for MFIS-FeFETs at Optimal Timing With Robust Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02%), and Self-Tracking Circuit Design

Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures

Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

First Demonstration of Ferroelectric Tunnel Thin-Film Transistor Nonvolatile Memory With Polycrystalline-Silicon Channel and HfZrO } Gate Dielectric

Impact of Nanosheet Thickness on Performance and Reliability of Polycrystalline-Silicon Thin-Film Transistors With Double-Gate Operation

Monolithically Integrated Polysilicon/Oxide-Semiconductor Hybrid Thin-Film Transistors for Advanced Sensing

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model

Effects of Annealing Temperature on TiN/Hf0.5Zr0.5O2/TiN Ferroelectric Capacitor Prepared by In-Situ Like Consecutive Atomic Layer Deposition

Effective N-methyl-2-pyrrolidone wet cleaning for fabricating high-performance monolayer MoS2 transistors

Steep-slope hysteresis-free negative capacitance MoS2 transistors

Identification of the scraping quality for the machine tool using the smartphone

Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET

Enhancement of Ferroelectricity in 5 nm Metal-Ferroelectric-Insulator Technologies by Using a Strained TiN Electrode

Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications

3-D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM

DC-free Method to Evaluate Nanoscale Equivalent Oxide Thickness: Dark-Mode Scanning Capacitance Microscopy

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Trapping Depth and Transition Probability of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor

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