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Online Fault Tolerance for FPGA Logic Blocks

IEEE transactions on very large scale integration (VLSI) systems, 2007-02, Vol.15 (2), p.216-226

2007

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Online BIST and BIST-based diagnosis of FPGA logic blocks

IEEE transactions on very large scale integration (VLSI) systems, 2004-12, Vol.12 (12), p.1284-1294

2004

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BIST-based test and diagnosis of FPGA logic blocks

IEEE transactions on very large scale integration (VLSI) systems, 2001-02, Vol.9 (1), p.159-172

2001

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FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems

IEEE transactions on industrial electronics (1982), 2007-08, Vol.54 (4), p.1885-1897

2007

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Built-In Self-Test of configurable logic blocks in Virtex-5 FPGAs

2009 41st Southeastern Symposium on System Theory, 2009, p.230-234

2009

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Soft Core Embedded Processor Based Built-In Self-Test of FPGAs

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009, p.29-37

2009

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Built-In Self-Test of digital signal processors in Virtex-4 FPGAs

2009 41st Southeastern Symposium on System Theory, 2009, p.34-38

2009

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Built-In Self-Test of programmable input/output tiles in Virtex-5 FPGAs

2009 41st Southeastern Symposium on System Theory, 2009, p.235-239

2009

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Reliability of majority voting based VLSI fault-tolerant circuits

IEEE transactions on very large scale integration (VLSI) systems, 1994-12, Vol.2 (4), p.516-521

Stroud, C.E.

1994

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Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009, p.11-19

2009

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Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems

Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001, 2001, p.73-92

2001

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Bist for minx 4000 and spartan series fpgas: a case study

International Test Conference, 2003. Proceedings. ITC 2003, 2003, Vol.1, p.1258-1267

2003

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Automated BIST for sequential logic synthesis

IEEE design & test of computers, 1988-12, Vol.5 (6), p.22-32

Stroud, C.E.

1988

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Bridging fault extraction from physical design data for manufacturing test development

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), 2000, p.760-769

2000

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Yield modeling for majority voting based defect-tolerant VLSI circuits

Proceedings IEEE Southeastcon'99. Technology on the Brink of 2000 (Cat. No.99CH36300), 1999, p.229-236

Stroud, C.E.

1999

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Improving the efficiency of error identification via signature analysis

Proceedings 13th IEEE VLSI Test Symposium, 1995, p.244-249

1995

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PARVOVIRUS INFECTIONS AND HYPOPLASTIC CRISIS IN SICKLE-CELL ANAEMIA

The Lancet (British edition), 1981-03, Vol.317 (8221), p.664-665

1981

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An automated BIST approach for general sequential logic synthesis

25th ACM/IEEE, Design Automation Conference.Proceedings 1988, 1988, p.3-8

Stroud, C.E.

1988

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Applying built-in self-test to majority voting fault tolerant circuits

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231), 1998, p.303-308

1998

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Built-in self-test for high-speed data-path circuitry

1991, Proceedings. International Test Conference, 1991, p.47-56

Stroud, C.E.

1991

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DISTRACTIONS IN DESIGN FOR TESTABILITY AND BUILT-IN SELF-TEST

1991, Proceedings. International Test Conference, 1991, p.1112

Stroud, C.E.

1991

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Computer-aided design-verification vector generation

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit, 1994, p.144-147

1994

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An ASIC level BIST implementation for system level testing

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, 1991, p.P6-4/1

1991

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Reliability, testability and yield of majority voting VLSI

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit, 1990, p.P9/5.1-P9/5.4

1990

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Design for testability and test generation for static redundancy system level fault-tolerant circuits

Proceedings. 'Meeting the Tests of Time'., International Test Conference, 1989, p.812-818

1989

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Online Fault Tolerance for FPGA Logic Blocks

Online BIST and BIST-based diagnosis of FPGA logic blocks

BIST-based test and diagnosis of FPGA logic blocks

FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems

Built-In Self-Test of configurable logic blocks in Virtex-5 FPGAs

Soft Core Embedded Processor Based Built-In Self-Test of FPGAs

Built-In Self-Test of digital signal processors in Virtex-4 FPGAs

Built-In Self-Test of programmable input/output tiles in Virtex-5 FPGAs

Reliability of majority voting based VLSI fault-tolerant circuits

Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems

Roving STARs: an integrated approach to on-line testing, diagnosis, and fault tolerance for FPGAs in adaptive computing systems

Bist for minx 4000 and spartan series fpgas: a case study

Automated BIST for sequential logic synthesis

Bridging fault extraction from physical design data for manufacturing test development

Yield modeling for majority voting based defect-tolerant VLSI circuits

Improving the efficiency of error identification via signature analysis

PARVOVIRUS INFECTIONS AND HYPOPLASTIC CRISIS IN SICKLE-CELL ANAEMIA

An automated BIST approach for general sequential logic synthesis

Applying built-in self-test to majority voting fault tolerant circuits

Built-in self-test for high-speed data-path circuitry

DISTRACTIONS IN DESIGN FOR TESTABILITY AND BUILT-IN SELF-TEST

Computer-aided design-verification vector generation

An ASIC level BIST implementation for system level testing

Reliability, testability and yield of majority voting VLSI

Design for testability and test generation for static redundancy system level fault-tolerant circuits

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