UB Paderborn / Katalog / Suche / in CDI

Path delay fault diagnosis and coverage-a metric and an estimation technique

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-03, Vol.20 (3), p.440-457

2001

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Perspectives on technology and technology-driven CAD

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-12, Vol.19 (12), p.1544-1560

2000

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Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-04, Vol.29 (4), p.509-527

2010

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In-line defect sampling methodology in yield management: an integrated framework

IEEE transactions on semiconductor manufacturing, 1996-11, Vol.9 (4), p.506-517

1996

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Global and local congestion optimization in technology mapping

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-04, Vol.22 (4), p.498-505

2003

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Primitive path delay faults: identification and their use in timing analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-11, Vol.19 (11), p.1347-1362

2000

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METRO-3D: an efficient three-dimensional wafer inspection simulator for next-generation lithography

IEEE transactions on semiconductor manufacturing, 2004-11, Vol.17 (4), p.619-628

2004

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In-line yield prediction methodologies using patterned wafer inspection information

IEEE transactions on semiconductor manufacturing, 1998-02, Vol.11 (1), p.40-47

1998

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Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes

2006 IEEE International Symposium on Semiconductor Manufacturing, 2006, p.xxiii-xxxii

Strojwas, A.J.

2006

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METRO-3D: an efficient three-dimensional wafer inspection simulator for next generation lithography

13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259), 2002, p.396-401

2002

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Correlation-aware statistical timing analysis with non-gaussian delay distributions

Proceedings of the 42nd annual Design Automation Conference, 2005, p.77-82

2005

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A Methodology for Worst-Case Analysis of Integrated Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1986-01, Vol.5 (1), p.104-113

1986

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Design methodology for IC manufacturability based on regular logic-bricks

Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005, 2005, p.353-358

2005

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Exploring regular fabrics to optimize the performance-cost trade-off

Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003, 2003, p.782-787

2003

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Routing architecture exploration for regular fabrics

Annual ACM IEEE Design Automation Conference: Proceedings of the 41st annual conference on Design automation; 07-11 June 2004, 2004, p.204-207

2004

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Effective excursion detection by defect type grouping in in-line inspection and classification

IEEE transactions on semiconductor manufacturing, 1999-02, Vol.12 (1), p.3-10

1999

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Design for manufacturability in nanometer era: system implementation and silicon results

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.268-269 Vol. 1

2005

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Congestion-aware logic synthesis

Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002, 2002, p.664-671

2002

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Ftd: frequency to time domain conversion for reduced-order interconnect simulation

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2001-04, Vol.48 (4), p.500-506

2001

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Guest Editors' Introduction: DFM Drives Changes in Design Flow

IEEE design & test of computers, 2005-05, Vol.22 (3), p.200-205

2005

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Taking the next step in moore's law: Designs turn to enable next technology node

2008 IEEE International Electron Devices Meeting, 2008, p.1-1

Strojwas, A.J.

2008

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Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults

Proceedings of International Conference on Computer Aided Design, 1996, p.494-501

1996

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Design-manufacturing interface for 0.13 um and below

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004, p.774-774

Strojwas, A.J.

2004

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Editorial

IEEE transactions on computer-aided design of integrated circuits and systems, 1987-03, Vol.6 (2), p.158-158

Strojwas, A.J.

1987

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Editorial

IEEE transactions on computer-aided design of integrated circuits and systems, 1987-03, Vol.6 (2), p.158-158

Strojwas, A.J.

1987

Volltextzugriff (PDF)

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Path delay fault diagnosis and coverage-a metric and an estimation technique

Perspectives on technology and technology-driven CAD

Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

In-line defect sampling methodology in yield management: an integrated framework

Global and local congestion optimization in technology mapping

Primitive path delay faults: identification and their use in timing analysis

METRO-3D: an efficient three-dimensional wafer inspection simulator for next-generation lithography

In-line yield prediction methodologies using patterned wafer inspection information

Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes

METRO-3D: an efficient three-dimensional wafer inspection simulator for next generation lithography

Correlation-aware statistical timing analysis with non-gaussian delay distributions

A Methodology for Worst-Case Analysis of Integrated Circuits

Design methodology for IC manufacturability based on regular logic-bricks

Exploring regular fabrics to optimize the performance-cost trade-off

Routing architecture exploration for regular fabrics

Effective excursion detection by defect type grouping in in-line inspection and classification

Design for manufacturability in nanometer era: system implementation and silicon results

Congestion-aware logic synthesis

Ftd: frequency to time domain conversion for reduced-order interconnect simulation

Guest Editors' Introduction: DFM Drives Changes in Design Flow

Taking the next step in moore's law: Designs turn to enable next technology node

Delay fault coverage: a realistic metric and an estimation technique for distributed path delay faults

Design-manufacturing interface for 0.13 um and below

Editorial

Editorial

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