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Statistical model checking of approximate circuits: challenges and opportunities

Proceedings of the 23rd Conference on Design, Automation and Test in Europe, 2020, p.1574-1577

Strnadel, Josef

2020

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Statistical Model Checking of Approximate Circuits: Challenges and Opportunities

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020, p.1574-1577

Strnadel, Josef

2020

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Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.614-617

Strnadel, Josef

2019

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On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle

Leveraging Applications of Formal Methods, Verification and Validation: Foundational Techniques, p.166-181

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Statistical Model Checking of Processor Systems in Various Interrupt Scenarios

Leveraging Applications of Formal Methods, Verification and Validation. Verification, p.414-429

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Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates

Architecture of Computing Systems – ARCS 2013, p.98-109

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Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking

2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2022, p.88-93

Strnadel, Josef

2022

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Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults

2021 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2021, p.111-114

Strnadel, Josef

2021

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Reflecting RTOS Model During WCET Timing Analysis: MSP430/Freertos Case Study

Acta electrotechnica et informatica, 2012-12, Vol.12 (4), p.17-29

2012

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On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking

2017 Euromicro Conference on Digital System Design (DSD), 2017, p.352-355

Strnadel, Josef

2017

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Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads

2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems, 2015, p.39-44

Strnadel, Josef

2015

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The Use of Genetic Algorithm to Reduce Power Consumption during Test Application

Evolvable Systems: From Biology to Hardware, p.181-192

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On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC

2016 Austrochip Workshop on Microelectronics (Austrochip), 2016, p.45-50

2016

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On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2013, p.24-29

Strnadel, J.

2013

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Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012, p.121-126

Strnadel, J.

2012

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Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework

2014 17th Euromicro Conference on Digital System Design, 2014, p.333-340

2014

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Automatic discovery of RTL benchmark circuits with predefined testability properties

2005 NASA/DoD Conference on Evolvable Hardware (EH'05), 2005, p.51-58

2005

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TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008, p.865-872

Strnadel, J.

2008

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On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels

2012 15th Euromicro Conference on Digital System Design, 2012, p.272-279

2012

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Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space

2006 IEEE Design and Diagnostics of Electronic Circuits and systems, 2006, p.159-160

Strnadel, J.

2006

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Nested Loops Degree Impact on RTL Digital Circuit Testability 1

IFAC Proceedings Volumes, 2003-02, Vol.36 (1), p.213-218

Strnadel, Josef

2003

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Nested Loops Degree Impact on RTL Digital Circuit Testability1

IFAC Proceedings Volumes, 2003-02, Vol.36 (1), p.213-218

Strnadel, Josef

2003

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On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

2011 14th Euromicro Conference on Digital System Design, 2011, p.367-374

2011

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Reduction of power dissipation through parallel optimization of test vector and scan register sequences

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010, p.364-369

2010

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The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010, p.644-651

2010

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Statistical model checking of approximate circuits: challenges and opportunities

Statistical Model Checking of Approximate Circuits: Challenges and Opportunities

Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates

On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle

Statistical Model Checking of Processor Systems in Various Interrupt Scenarios

Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates

Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking

Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults

Reflecting RTOS Model During WCET Timing Analysis: MSP430/Freertos Case Study

On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking

Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads

The Use of Genetic Algorithm to Reduce Power Consumption during Test Application

On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC

On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems

Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems

Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework

Automatic discovery of RTL benchmark circuits with predefined testability properties

TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path

On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels

Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space

Nested Loops Degree Impact on RTL Digital Circuit Testability 1

Nested Loops Degree Impact on RTL Digital Circuit Testability1

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

Reduction of power dissipation through parallel optimization of test vector and scan register sequences

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

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