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A High-Performance System for Robust Stain Normalization of Whole-Slide Images in Histopathology

Frontiers in medicine, 2019-09, Vol.6, p.193

2019

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Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices

Frontiers in computational neuroscience, 2021-07, Vol.15, p.675741-675741

2021

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Circuit and System-Level Aspects of Phase Change Memory

IEEE transactions on circuits and systems. II, Express briefs, 2021-03, Vol.68 (3), p.844-850

2021

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Multilevel-Cell Phase-Change Memory: A Viable Technology

IEEE journal on emerging and selected topics in circuits and systems, 2016-03, Vol.6 (1), p.87-100

2016

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Phase Change Memory Reliability: A Signal Processing and Coding Perspective

IEEE transactions on magnetics, 2015-04, Vol.51 (4), p.1-7

2015

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A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh

IEEE transactions on very large scale integration (VLSI) systems, 2023-01, Vol.31 (1), p.114-127

2023

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High-Throughput ECC with Integrated Chipkill Protection for Nonvolatile Memory Arrays

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, p.1-5

2021

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HERMES-Core—A 1.59-TOPS/mm 2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

IEEE journal of solid-state circuits, 2022-04, Vol.57 (4), p.1027-1038

2022

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HERMES-Core-A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

IEEE journal of solid-state circuits, 2022-04, Vol.57 (4), p.1027-1038

2022

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Drift-Invariant Detection for Multilevel Phase-Change Memory

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures

2015 IEEE International Reliability Physics Symposium, 2015, p.5B.6.1-5B.6.6

2015

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Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash

2020 IEEE International Reliability Physics Symposium (IRPS), 2020, p.1-6

2020

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11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.212-214

2024

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A Fast and Scalable Pipeline for Stain Normalization of Whole-Slide Images in Histopathology

Computer Vision – ECCV 2018 Workshops, p.424-436

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Accelerated ML-Assisted Tumor Detection in High-Resolution Histopathology Images

Medical Image Computing and Computer Assisted Intervention – MICCAI 2019, p.406-414

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The complete time/temperature dependence of I-V drift in PCM devices

2016 IEEE International Reliability Physics Symposium (IRPS), 2016, p.MY-1-1-MY-1-6

2016

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Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

IEEE transactions on nanotechnology, 2009-05, Vol.8 (3), p.379-390

2009

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Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-4

2015

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Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009, p.340-348

2009

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On the Reliability of Post-CMOS and SET Systems

International journal of nanotechnology and molecular computation, 2009-04, Vol.1 (2), p.43-57

2009

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Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth

Nano-Net, p.70-75

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Selective redundancy-based design techniques for the minimization of local delay variations

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.2486-2489

2010

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Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect

2019 19th Non-Volatile Memory Technology Symposium (NVMTS), 2019, p.1-4

2019

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A High-Performance System for Robust Stain Normalization of Whole-Slide Images in Histopathology

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices

Circuit and System-Level Aspects of Phase Change Memory

Multilevel-Cell Phase-Change Memory: A Viable Technology

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

Phase Change Memory Reliability: A Signal Processing and Coding Perspective

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh

High-Throughput ECC with Integrated Chipkill Protection for Nonvolatile Memory Arrays

HERMES-Core—A 1.59-TOPS/mm 2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core-A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Drift-Invariant Detection for Multilevel Phase-Change Memory

Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor

Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures

Open Block Characterization and Read Voltage Calibration of 3D QLC NAND Flash

11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge

A Fast and Scalable Pipeline for Stain Normalization of Whole-Slide Images in Histopathology

Accelerated ML-Assisted Tumor Detection in High-Resolution Histopathology Images

The complete time/temperature dependence of I-V drift in PCM devices

Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)

On the Reliability of Post-CMOS and SET Systems

Optimization of Nanoelectronic Systems Reliability by Reducing Logic Depth

Selective redundancy-based design techniques for the minimization of local delay variations

Reliability of 3D NAND flash memory with a focus on read voltage calibration from a system aspect

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