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Voltage Reduced Self Refresh (VRSR) for optimized energy savings in DRAM Memories

Memories - Materials, Devices, Circuits and Systems, 2023-07, Vol.4, p.100058, Article 100058

2023

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Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs

IEEE transactions on nanotechnology, 2018-07, Vol.17 (4), p.772-782

2018

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Architecture slack exploitation for phase classification and performance estimation in server-class processors

Journal of parallel and distributed computing, 2022-11, Vol.169, p.157-170

2022

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A low-complexity and robust minimum variance beamformer for ultrasound imaging systems using beamspace dominant mode rejection

Ultrasonics, 2020-02, Vol.101, p.105979-105979, Article 105979

2020

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A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles

IEEE transactions on industrial informatics, 2020-05, Vol.16 (5), p.3335-3344

2020

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An ESOP Based Cube Decomposition Technique for Reversible Circuits

Reversible Computation, p.127-140

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Cluster Based Energy Efficient Routing Protocol Using ANT Colony Optimization and Breadth First Search

Procedia computer science, 2016, Vol.89, p.124-133

2016

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Early detection of glaucoma: feature visualization with a deep convolutional network

Computer methods in biomechanics and biomedical engineering., 2024-12, Vol.12 (1)

2024

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Improved designs of digit-by-digit decimal multiplier

Integration (Amsterdam), 2018-03, Vol.61, p.150-159

2018

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A Soft Computing Approach for Data Routing in Hospital Area Networks (HAN)

International journal of business data communications and networking, 2016-07, Vol.12 (2), p.16-27

2016

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Glaucoma - Automating the Cup-to-Disc Ratio Estimation in Fundus Images by Combining Random Walk Algorithm with Otsu Thresholding

2021 10th International IEEE/EMBS Conference on Neural Engineering (NER), 2021, p.154-157

2021

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An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018, p.19-24

2018

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Dielectric loss behavior of liquid nitrogen in uniform fields: Millimeter gap

IEEE transactions on dielectrics and electrical insulation, 2000-04, Vol.7 (2), p.296-302

2000

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Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007, p.324-329

2007

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Energy efficient design of CNFET-based multi-digit ternary adders

Microelectronics, 2018-05, Vol.75, p.75-86

2018

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Novel BCD adders and their reversible logic implementation for IEEE 754r format

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006, p.6 pp.

2006

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Design of a Low Power, Variable-Resolution Flash ADC

2009 22nd International Conference on VLSI Design, 2009, p.117-122

2009

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An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

2010 23rd International Conference on VLSI Design, 2010, p.411-416

2010

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Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks

International journal on smart sensing and intelligent systems, 2008-12, Vol.1 (4), p.912-921

2008

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A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC

2007 IFIP International Conference on Very Large Scale Integration, 2007, p.252-257

2007

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High-Throughput Montgomery Modular Multiplication

2006 IFIP International Conference on Very Large Scale Integration, 2006, p.58-62

2006

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Novel design and reversible logic synthesis of multiplexer based full adder and multipliers

48th Midwest Symposium on Circuits and Systems, 2005, 2005, p.1593-1596 Vol. 2

2005

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Delay and slew analysis of VLSI interconnects using difference model approach

2007 50th Midwest Symposium on Circuits and Systems, 2007, p.1313-1315

2007

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An efficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics

48th Midwest Symposium on Circuits and Systems, 2005, 2005, p.826-828 Vol. 1

2005

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Novel High-Speed Architecture for 32-Bit Binary Coded Decimal (BCD) Multiplier

2008 International Symposium on Communications and Information Technologies, 2008, p.543-546

2008

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Voltage Reduced Self Refresh (VRSR) for optimized energy savings in DRAM Memories

Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs

Architecture slack exploitation for phase classification and performance estimation in server-class processors

A low-complexity and robust minimum variance beamformer for ultrasound imaging systems using beamspace dominant mode rejection

A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles

An ESOP Based Cube Decomposition Technique for Reversible Circuits

Cluster Based Energy Efficient Routing Protocol Using ANT Colony Optimization and Breadth First Search

Early detection of glaucoma: feature visualization with a deep convolutional network

Improved designs of digit-by-digit decimal multiplier

A Soft Computing Approach for Data Routing in Hospital Area Networks (HAN)

Glaucoma - Automating the Cup-to-Disc Ratio Estimation in Fundus Images by Combining Random Walk Algorithm with Otsu Thresholding

An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications

Dielectric loss behavior of liquid nitrogen in uniform fields: Millimeter gap

Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors

Energy efficient design of CNFET-based multi-digit ternary adders

Novel BCD adders and their reversible logic implementation for IEEE 754r format

Design of a Low Power, Variable-Resolution Flash ADC

An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks

A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC

High-Throughput Montgomery Modular Multiplication

Novel design and reversible logic synthesis of multiplexer based full adder and multipliers

Delay and slew analysis of VLSI interconnects using difference model approach

An efficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics

Novel High-Speed Architecture for 32-Bit Binary Coded Decimal (BCD) Multiplier

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