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Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node

IEEE transactions on electron devices, 2022-08, Vol.69 (8), p.4115-4122

2022

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Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

IEEE access, 2023, Vol.11, p.90421-90429

2023

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Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective

IEEE access, 2024, Vol.12, p.9563-9571

2024

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Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

International journal of RF and microwave computer-aided engineering, 2021-12, Vol.31 (12), p.n/a

2021

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Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

ECS journal of solid state science and technology, 2021-01, Vol.10 (1), p.13008

2021

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Analog and mixed circuit analysis of nanosheet FET at elevated temperatures

Physica scripta, 2023-10, Vol.98 (10), p.105409

2023

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Concurrent error detectable and self-repairable carry select adder

International journal of electronics, 2022-11, Vol.109 (11), p.1954-1972

2022

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Spacer engineering on multi-channel FinFET for advanced wireless applications

International journal of electronics and communications, 2024-05, Vol.178, p.155298, Article 155298

2024

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An intensive study on organic thin film transistors (OTFTs) for future flexible/wearable electronics applications

Micro and nanostructures (2022), 2024-03, Vol.187, p.207766, Article 207766

2024

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Design of approximate reverse carry select adder using RCPA

International journal of electronics letters, 2023-04, Vol.11 (2), p.146-156

2023

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Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

SILICON, 2022-06, Vol.14 (8), p.3823-3834

2022

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A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length

SILICON, 2022-04, Vol.14 (5), p.2009-2021

2022

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Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes

International journal of electronics and communications, 2022-02, Vol.145, p.154069, Article 154069

2022

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Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length

International journal of electronics and communications, 2021-07, Vol.137, p.153803, Article 153803

2021

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Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling

SILICON, 2022-08, Vol.14 (13), p.7461-7471

2022

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Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

SILICON, 2022-11, Vol.14 (16), p.10401-10411

2022

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Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

ECS journal of solid state science and technology, 2023-03, Vol.12 (3), p.33001

2023

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Design of Resistive Load Inverter and Common Source Amplifier Circuits Using Symmetric and Asymmetric Nanowire FETs

Journal of electronic materials, 2023-11, Vol.52 (11), p.7268-7279

2023

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Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic applications

Microelectronics, 2023-10, Vol.140, p.105923, Article 105923

2023

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Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

Microelectronics, 2021-10, Vol.116, p.105214, Article 105214

2021

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Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

ECS journal of solid state science and technology, 2023-02, Vol.12 (2), p.23013

2023

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Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

ECS journal of solid state science and technology, 2023-11, Vol.12 (11), p.113008

2023

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Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

ECS journal of solid state science and technology, 2023-05, Vol.12 (5), p.53009

2023

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Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs

2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT), 2022, p.1-5

2022

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Device Analysis of Vertically Stacked GAA Nanosheet FET at Advanced Technology Node

2023 3rd International Conference on Advances in Computing, Communication, Embedded and Secure Systems (ACCESS), 2023, p.274-279

2023

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Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison

Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective

Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications

Design and Deep Insights into Sub-10 nm Spacer Engineered Junctionless FinFET for Nanoscale Applications

Analog and mixed circuit analysis of nanosheet FET at elevated temperatures

Concurrent error detectable and self-repairable carry select adder

Spacer engineering on multi-channel FinFET for advanced wireless applications

An intensive study on organic thin film transistors (OTFTs) for future flexible/wearable electronics applications

Design of approximate reverse carry select adder using RCPA

Design and Temperature Assessment of Junctionless Nanosheet FET for Nanoscale Applications

A Comprehensive Analysis of Junctionless Tri-Gate (TG) FinFET Towards Low-Power and High-Frequency Applications at 5-nm Gate Length

Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes

Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length

Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling

Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

Impact of Scaling on Nanosheet FET and CMOS Circuit Applications

Design of Resistive Load Inverter and Common Source Amplifier Circuits Using Symmetric and Asymmetric Nanowire FETs

Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic applications

Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes

Common Source Amplifier and Ring Oscillator Circuit Performance Optimization Using Multi-Bridge Channel FETs

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs

Device Analysis of Vertically Stacked GAA Nanosheet FET at Advanced Technology Node

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