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Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016

Microprocessors and microsystems, 2018-07, Vol.60, p.38-39

Sparsø, Jens

2018

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PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments

IEEE transactions on very large scale integration (VLSI) systems, 2024-01, Vol.32 (1), p.150-163

2024

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Comparing timed-division multiplexing and best-effort networks-on-chip

Journal of systems architecture, 2022-12, Vol.133, p.102766, Article 102766

2022

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A time-predictable open-source TTEthernet end-system

Journal of systems architecture, 2020-09, Vol.108, p.101744, Article 101744

2020

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Using dynamic partial reconfiguration of FPGAs in real-Time systems

Microprocessors and microsystems, 2018-09, Vol.61, p.198-206

2018

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Hardlock: Real-time multicore locking

Journal of systems architecture, 2019-08, Vol.97, p.467-476

2019

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A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

Design, Automation and Test in Europe, 2005, p.1226-1231

2005

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Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014, p.45-52

2014

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A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

Journal of systems architecture, 2017-03, Vol.74, p.1-13

2017

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An area-efficient network interface for a TDM-based Network-on-Chip

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.1044-1047

2013

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Scratchpad Memories with Ownership

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.1216-1221

2019

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A Minimal Network Interface for a Simple Network-on-Chip

Architecture of Computing Systems – ARCS 2019, p.295-307

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A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip

2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2014, p.309-316

2014

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T-CREST: Time-predictable multi-core architecture for embedded systems

Journal of systems architecture, 2015-10, Vol.61 (9), p.449-471

2015

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Message Passing on a Time-predictable Multicore Processor

2015 IEEE 18th International Symposium on Real-Time Distributed Computing, 2015, p.51-59

2015

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The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation

ACM transactions on embedded computing systems, 2011-11, Vol.10 (4), p.1-26

2011

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Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

IEEE transactions on very large scale integration (VLSI) systems, 2009-02, Vol.17 (2), p.248-261

2009

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Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.479-492

2016

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Evaluating a Time-Triggered Runtime System by Distributing a Flight Controller

2021 26th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA ), 2021, p.1-8

2021

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Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid

Proceedings of the IEEE, 1999-02, Vol.87 (2), p.268-281

1999

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Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking

2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), 2019, p.9-18

2019

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Message from the Chairs - ASYNC 2012

2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, 2012, p.viii-ix

2012

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Analytical derivation of traffic patterns in cache-coherent shared-memory systems

Microprocessors and microsystems, 2011-10, Vol.35 (7), p.632-642

2011

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A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks

2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5

2023

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Synchronizing Real-Time Tasks in Time-Triggered Networks

2021 IEEE 24th International Symposium on Real-Time Distributed Computing (ISORC), 2021, p.11-19

2021

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Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments

Comparing timed-division multiplexing and best-effort networks-on-chip

A time-predictable open-source TTEthernet end-system

Using dynamic partial reconfiguration of FPGAs in real-Time systems

Hardlock: Real-time multicore locking

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

An area-efficient network interface for a TDM-based Network-on-Chip

Scratchpad Memories with Ownership

A Minimal Network Interface for a Simple Network-on-Chip

A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip

T-CREST: Time-predictable multi-core architecture for embedded systems

Message Passing on a Time-predictable Multicore Processor

The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

Evaluating a Time-Triggered Runtime System by Distributing a Flight Controller

Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid

Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking

Message from the Chairs - ASYNC 2012

Analytical derivation of traffic patterns in cache-coherent shared-memory systems

A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks

Synchronizing Real-Time Tasks in Time-Triggered Networks

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