UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 87

Sortiert nach

T-CREST: Time-predictable multi-core architecture for embedded systems

Journal of systems architecture, 2015-10, Vol.61 (9), p.449-471

2015

Link zum Volltext

Verfügbarkeit prüfen

Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016

Microprocessors and microsystems, 2018-07, Vol.60, p.38-39

Sparsø, Jens

2018

Link zum Volltext

Verfügbarkeit prüfen

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments

IEEE transactions on very large scale integration (VLSI) systems, 2024-01, Vol.32 (1), p.150-163

2024

Link zum Volltext
IEEE_Xplore

Comparing timed-division multiplexing and best-effort networks-on-chip

Journal of systems architecture, 2022-12, Vol.133, p.102766, Article 102766

2022

Link zum Volltext

Verfügbarkeit prüfen

A time-predictable open-source TTEthernet end-system

Journal of systems architecture, 2020-09, Vol.108, p.101744, Article 101744

2020

Link zum Volltext

Verfügbarkeit prüfen

Using dynamic partial reconfiguration of FPGAs in real-Time systems

Microprocessors and microsystems, 2018-09, Vol.61, p.198-206

2018

Link zum Volltext

Verfügbarkeit prüfen

Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

2010 IEEE Symposium on Asynchronous Circuits and Systems, 2010, p.41-51

2010

Link zum Volltext
IEEE_Xplore

Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014, p.45-52

2014

Link zum Volltext
IEEE_Xplore

An area-efficient network interface for a TDM-based Network-on-Chip

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, p.1044-1047

2013

Link zum Volltext
IEEE_Xplore

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

Journal of systems architecture, 2017-03, Vol.74, p.1-13

2017

Link zum Volltext

Verfügbarkeit prüfen

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

Design, Automation and Test in Europe, 2005, p.1226-1231

2005

Link zum Volltext
IEEE_Xplore

Scratchpad Memories with Ownership

2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019, p.1216-1221

2019

Link zum Volltext
IEEE_Xplore

A Reactive and Cycle-True IP Emulator for MPSoC Exploration

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-01, Vol.27 (1), p.109-122

2008

Link zum Volltext
IEEE_Xplore

A Minimal Network Interface for a Simple Network-on-Chip

Architecture of Computing Systems – ARCS 2019, p.295-307

Link zum Volltext

Verfügbarkeit prüfen

Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip

2012 12th International Conference on Application of Concurrency to System Design, 2012, p.1-5

Sparso, J.

2012

Link zum Volltext
IEEE_Xplore

Message Passing on a Time-predictable Multicore Processor

2015 IEEE 18th International Symposium on Real-Time Distributed Computing, 2015, p.51-59

2015

Link zum Volltext

Verfügbarkeit prüfen

The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation

ACM transactions on embedded computing systems, 2011-11, Vol.10 (4), p.1-26

2011

Link zum Volltext

Verfügbarkeit prüfen

A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip

2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2014, p.309-316

2014

Link zum Volltext

Verfügbarkeit prüfen

A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Design, Automation and Test in Europe, 2005, p.780-785

2005

Link zum Volltext
IEEE_Xplore

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

IEEE transactions on very large scale integration (VLSI) systems, 2009-02, Vol.17 (2), p.248-261

2009

Link zum Volltext
IEEE_Xplore

Message from the Chairs - ASYNC 2012

2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, 2012, p.viii-ix

2012

Link zum Volltext
IEEE_Xplore

Analytical derivation of traffic patterns in cache-coherent shared-memory systems

Microprocessors and microsystems, 2011-10, Vol.35 (7), p.632-642

2011

Link zum Volltext

Verfügbarkeit prüfen

Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid

Proceedings of the IEEE, 1999-02, Vol.87 (2), p.268-281

1999

Link zum Volltext
IEEE_Xplore

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.479-492

2016

Link zum Volltext
IEEE_Xplore

Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol

Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018, p.51-60

2018

Link zum Volltext

Verfügbarkeit prüfen

1 – 25 von 87

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(20)
Mit Volltextzugriff
(69)

Publikationsform

Sprache

Englisch
(87)
Japanisch
(3)

Erscheinungsjahr

n.n

Thema

Science & Technology
(52)
Technology
(50)
Computer Science
(45)
Computer Science, Hardware & Architecture
(34)
Engineering
(33)
Engineering, Electrical & Electronic
(33)
Clocks
(23)
Real-Time Systems
(22)
Computer Science, Theory & Methods
(18)
Time Division Multiplexing
(18)
Hardware
(16)
Schedules
(13)
Synchronization
(13)
Network-On-A-Chip
(12)
Computer Science, Software Engineering
(11)
Network-On-Chip
(11)
Asynchronous Circuits
(9)
Program Processors
(9)
Routing
(9)
Bandwidth
(8)

15 weitere anzeigen...

Weniger anzeigen...

Menü

Weitere Dienste

Einstellungen

T-CREST: Time-predictable multi-core architecture for embedded systems

Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016

PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments

Comparing timed-division multiplexing and best-effort networks-on-chip

A time-predictable open-source TTEthernet end-system

Using dynamic partial reconfiguration of FPGAs in real-Time systems

Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers

An area-efficient network interface for a TDM-based Network-on-Chip

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

Scratchpad Memories with Ownership

A Reactive and Cycle-True IP Emulator for MPSoC Exploration

A Minimal Network Interface for a Simple Network-on-Chip

Design of Networks-on-Chip for Real-Time Multi-processor Systems-on-Chip

Message Passing on a Time-predictable Multicore Processor

The ReNoC Reconfigurable Network-on-Chip: Architecture, Configuration Algorithms, and Evaluation

A Metaheuristic Scheduler for Time Division Multiplexed Networks-on-Chip

A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

Message from the Chairs - ASYNC 2012

Analytical derivation of traffic patterns in cache-coherent shared-memory systems

Designing asynchronous circuits for low power: an IFIR filter bank for a digital hearing aid

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

Hardware Assisted Clock Synchronization with the IEEE 1588-2008 Precision Time Protocol

Suchergebnisse filtern