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A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

IEEE journal of solid-state circuits, 2008-07, Vol.43 (7), p.1542-1552

2008

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A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

IEEE journal of solid-state circuits, 2009-06, Vol.44 (6), p.1668-1678

2009

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A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity

IEEE journal of solid-state circuits, 2005-12, Vol.40 (12), p.2515-2524

2005

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A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

IEEE journal of solid-state circuits, 2006-06, Vol.41 (6), p.1323-1332

2006

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A sub-130-nm conditional keeper technique

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.633-638

2002

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A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

IEEE journal of solid-state circuits, 2006-08, Vol.41 (8), p.1757-1763

2006

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Desensitized CMOS Low-Noise Amplifiers

IEEE transactions on circuits and systems. I, Regular papers, 2008-04, Vol.55 (3), p.752-765

2008

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A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.624-632

2002

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A 130-nm 6-GHz 256x32 bit leakage-tolerant register file

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.624

2002

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A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

IEEE journal of solid-state circuits, 2011-07, Vol.46 (7), p.1596-1605

2011

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Low voltage techniques for sub 100nm CMOS, RF transceivers

2005 IEEE Radio Frequency integrated Circuits (RFIC) Symposium - Digest of Papers, 2005, p.501-504

Soumyanath, K.

2005

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Measurement and modeling errors in noise parameters of scaled-CMOS devices

IEEE transactions on microwave theory and techniques, 2006-06, Vol.54 (6), p.2336-2345

2006

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A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

2010 Symposium on VLSI Technology, 2010, p.137-138

2010

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Accurate on-chip interconnect evaluation: a time-domain technique

IEEE journal of solid-state circuits, 1999-05, Vol.34 (5), p.623-631

1999

Volltextzugriff (PDF)

Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends

IEEE journal of solid-state circuits, 2001-11, Vol.36 (11), p.1636-1646

2001

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5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS

IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1421

2002

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A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.76-77,77a

2009

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Sub-500ps 64b ALUs in 0.18 mu m SOI/bulk CMOS: Design & scaling trends

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2001

2001

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9)

2004

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A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.91-103

2013

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A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop

Digest of technical papers - IEEE International Solid-State Circuits Conference, 2002-01, p.332-333+534

2002

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Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process

IEEE journal of solid-state circuits, 2004-09, Vol.39 (9), p.1536-1543

2004

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RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

2010 International Electron Devices Meeting, 2010, p.27.2.1-27.2.4

2010

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A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, p.496-631

2008

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An analog scheme for fixed-point computation-Part II: Applications

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 1999-04, Vol.46 (4), p.442-451

1999

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A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A sub-130-nm conditional keeper technique

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process

Desensitized CMOS Low-Noise Amplifiers

A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

A 130-nm 6-GHz 256x32 bit leakage-tolerant register file

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

Low voltage techniques for sub 100nm CMOS, RF transceivers

Measurement and modeling errors in noise parameters of scaled-CMOS devices

A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

Accurate on-chip interconnect evaluation: a time-domain technique

Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS

A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS

Sub-500ps 64b ALUs in 0.18 mu m SOI/bulk CMOS: Design & scaling trends

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V sub(T) CMOS process

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/T/ CMOS process

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

A 28mW Spectrum-Sensing Reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11n/WiMAX Receivers

An analog scheme for fixed-point computation-Part II: Applications

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