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ARB: a hardware mechanism for dynamic reordering of memory references

IEEE transactions on computers, 1996-05, Vol.45 (5), p.552-571

1996

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Speculative multithreaded processors

Computer (Long Beach, Calif.), 2001-04, Vol.34 (4), p.66-73

2001

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Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers

IEEE transactions on computers, 1990-03, Vol.39 (3), p.349-359

Sohi, G.S.

1990

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Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

Proceedings of the IEEE, 2001-11, Vol.89 (11), p.1560-1575

2001

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Speculative incoherent cache protocols

IEEE MICRO, 2004-11, Vol.24 (6), p.104-109

2004

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Evaluating design choices for shared bus multiprocessors in a throughput-oriented environment

IEEE transactions on computers, 1992-03, Vol.41 (3), p.297-317

1992

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Reducing memory latency via read-after-read memory dependence prediction

IEEE transactions on computers, 2002-03, Vol.51 (3), p.313-326

2002

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Supporting Overcommitted Virtual Machines through Hardware Spin Detection

IEEE transactions on parallel and distributed systems, 2012-02, Vol.23 (2), p.353-366

2012

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The pathologic correlates of the electrocardiogram: complete left bundle branch block

Circulation (New York, N.Y.), 1982-03, Vol.65 (3), p.445-451

1982

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Surface recording of His-Purkinje activity on an every-beat basis without digital averaging

Circulation (New York, N.Y.), 1981-04, Vol.63 (4), p.948-952

1981

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High-bandwidth interleaved memories for vector processors-a simulation study

IEEE transactions on computers, 1993-01, Vol.42 (1), p.34-44

Sohi, G.S.

1993

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Exploiting value locality in physical register files

Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36, 2003, p.265-276

2003

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Design and analysis of a gracefully degrading interleaved memory system

IEEE transactions on computers, 1990-01, Vol.39 (1), p.63-71

1990

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A Dynamic Electrical Record of the Pathway of Human His Bundle Activation from Surface Mapping

Circulation research, 1982-01, Vol.50 (1), p.47-54

1982

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Cache memory organization to enhance the yield of high performance VLSI processors

IEEE transactions on computers, 1989-04, Vol.38 (4), p.484-492

Sohi, G.S.

1989

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Body surface map patterns of altered depolarization and repolarization in right bundle branch block

Circulation (New York, N.Y.), 1980-03, Vol.61 (3), p.634-640

1980

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Distributed-directory scheme: scalable coherent interface

Computer (Long Beach, Calif.), 1990-06, Vol.23 (6), p.74-77

1990

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Guarded execution and branch prediction in dynamic ILP processors

International Symposium on Computer Architecture: Proceedings of the 21st annual international symposium on Computer architecture : Chicago, Illinois, United States; 18-21 Apr. 1994, 1994, p.120-129

1994

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The microarchitecture of superscalar processors

Proceedings of the IEEE, 1995-12, Vol.83 (12), p.1609-1624

1995

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Comparison of total body surface map depolarization patterns of left bundle branch block and normal axis with left bundle branch block and left-axis deviation

Circulation (New York, N.Y.), 1983-03, Vol.67 (3), p.660-664

1983

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Surface Reflections of Cardiac Excitation and the Assessment of Infarct Volume in Dogs: A Comparison of Methods

Circulation research, 1978-09, Vol.43 (3), p.406-413

1978

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A static power model for architects

Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000, 2000, p.191-201

2000

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Request combining in multiprocessors with arbitrary interconnection networks

IEEE transactions on parallel and distributed systems, 1994-11, Vol.5 (11), p.1140-1155

1994

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Body surface potential maps in patients with pulmonic valvular and aortic valvular stenosis of mild to moderate severity

Circulation (New York, N.Y.), 1979-06, Vol.59 (6), p.1277-1283

1979

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Irradiation-induced constrictive pericarditis requiring pericardiectomy during pregnancy

Journal of reproductive medicine, 1980-03, Vol.24 (3), p.127

1980

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ARB: a hardware mechanism for dynamic reordering of memory references

Speculative multithreaded processors

Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers

Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling

Speculative incoherent cache protocols

Evaluating design choices for shared bus multiprocessors in a throughput-oriented environment

Reducing memory latency via read-after-read memory dependence prediction

Supporting Overcommitted Virtual Machines through Hardware Spin Detection

The pathologic correlates of the electrocardiogram: complete left bundle branch block

Surface recording of His-Purkinje activity on an every-beat basis without digital averaging

High-bandwidth interleaved memories for vector processors-a simulation study

Exploiting value locality in physical register files

Design and analysis of a gracefully degrading interleaved memory system

A Dynamic Electrical Record of the Pathway of Human His Bundle Activation from Surface Mapping

Cache memory organization to enhance the yield of high performance VLSI processors

Body surface map patterns of altered depolarization and repolarization in right bundle branch block

Distributed-directory scheme: scalable coherent interface

Guarded execution and branch prediction in dynamic ILP processors

The microarchitecture of superscalar processors

Comparison of total body surface map depolarization patterns of left bundle branch block and normal axis with left bundle branch block and left-axis deviation

Surface Reflections of Cardiac Excitation and the Assessment of Infarct Volume in Dogs: A Comparison of Methods

A static power model for architects

Request combining in multiprocessors with arbitrary interconnection networks

Body surface potential maps in patients with pulmonic valvular and aortic valvular stenosis of mild to moderate severity

Irradiation-induced constrictive pericarditis requiring pericardiectomy during pregnancy

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