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TRANSDUCERS '03. 12th International Conference on Solid-State Sensors, Actuators and Microsystems. Digest of Technical Papers (Cat. No.03TH8664), 2003, Vol.2, p.1714-1717 vol.2

2003

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Test structures for the evaluation of 3D chip interconnection schemes

2008 IEEE International Conference on Microelectronic Test Structures, 2008, p.117-122

2008

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Integration of a temporary carrier in a TSV process flow

2009 59th Electronic Components and Technology Conference, 2009, p.865-871

2009

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Gold-tin bonding for 200mm wafer level hermetic MEMS packaging

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.1610-1615

2011

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Polymer filling of medium density through silicon via for 3D-packaging

2009 11th Electronics Packaging Technology Conference, 2009, p.790-794

2009

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Wafer level underfill entrapment in solder joint during thermocompression: Simulation and experimental validation

2013 IEEE 63rd Electronic Components and Technology Conference, 2013, p.768-772

2013

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Reliability study of 3D-WLP through silicon via with innovative polymer filling integration

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, p.567-572

2011

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RF characterization of the substrate coupling noise between TSV and active devices in 3D integrated circuits

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

Through Silicon Via technology using tungsten metallization

Assessment and Characterization of Stress Induced by Via-First TSV Technology

Micromachined mass spectrometer

System on Wafer: A New Silicon Concept in SiP

Process solutions and polymer materials for 3D-WLP through silicon via filling

System-on-Wafer: 2-D and 3-D Technologies for Heterogeneous Systems

Through silicon vias technology for CMOS image sensors packaging

Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs

Investigation on TSV impact on 65nm CMOS devices and circuits

"RF characterization and modeling of high density Through Silicon Vias for 3D chip stacking"

Effects of stress in polysilicon VIA - first TSV technology

Development and characterisation of a 3D technology including TSV and Cu pillars for high frequency applications

Through Silicon Via polymer filling for 3D-WLP applications

Cost effective dry lithography solution for through silicon via technology

Hermetic wafer-level packaging development for RF MEMS switch

TSV as an alternative to wire bonding for a wireless industrial product: another step towards 3D integration

Integrated RF-MEMS switch based on a combination of thermal and electrostatic actuation