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Process sensitivity and robustness analysis of via-first dual-damascene process

IEEE transactions on semiconductor manufacturing, 2003-05, Vol.16 (2), p.307-313

2003

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Effects of plasma treatment on the properties of room-temperature liquid-phase deposited (LPD) oxide films

Journal of non-crystalline solids, 1995-07, Vol.187, p.81-85

1995

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Thinner liquid phase deposited oxide for polysilicon thin-film transistors

IEEE electron device letters, 1995-11, Vol.16 (11), p.473-475

1995

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Plasma charging damage during contact hole etch in high-density plasma etcher

Microelectronics and reliability, 2000-12, Vol.40 (12), p.2039-2046

2000

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Performance and off-state current mechanisms of low-temperature processed polysilicon thin-film transistors with liquid phase deposited SiO2 gate insulator

IEEE transactions on electron devices, 1994-02, Vol.41 (2), p.173-179

1994

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Low-Temperature-Processed Poly-Si Thin-Film Transistors Using Solid-Phase-Crystallized and Liquid-Phase-Deposited Gate Oxide

Japanese Journal of Applied Physics, 1994, Vol.33 (4R), p.1798

1994

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Stress in Liquid‐Phase Deposited Oxide Films

Journal of the Electrochemical Society, 1996-08, Vol.143 (8), p.2658-2662

1996

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Low-temperature processed MOSFET's with liquid phase deposited SiO2-xFx as gate insulator

IEEE electron device letters, 1995-07, Vol.16 (7), p.316-318

1995

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Novel technique for SiO2 formed by liquid-phase deposition for low-temperature processed polysilicon TFT

IEEE electron device letters, 1993-08, Vol.14 (8), p.403-405

1993

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A 25-nm gate-length FinFET transistor module for 32nm node

2009 IEEE International Electron Devices Meeting (IEDM), 2009, p.1-4

2009

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A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

2010 International Electron Devices Meeting, 2010, p.34.1.1-34.1.4

2010

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Fabrication of MOSFETs using low-temperature liquid-phase deposited oxide

Microelectronic engineering, 1995-06, Vol.28 (1), p.101-104

1995

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Narrow Width and Length Dependence of SiGe and Sallow-Trench-Isolation Stress Induced Defects in 45 nm p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Strained SiGe Source/Drain

Japanese Journal of Applied Physics, 2009-04, Vol.48 (4S), p.4

2009

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A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.316-317

2013

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A test structure to verify the robustness of silicided N+/P+ interface

Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516), 2004, p.169-172

2004

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High quality thin oxide films formed by using ultra low temperature liquid phase deposition

International Electron Devices and Materials Symposium, 1994, p.11-11

1994

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Reverse CoSi 2 Thermal Stability and Digitized Sheet Resistance Increase of Sub-90 nm Polysilicon Lines

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2217

2005

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Low-temperature processed MOSFETs with liquid phase deposited SiO/sub 2-x/Fx as gate insulator

IEEE electron device letters, 1995-07, Vol.16 (7), p.316-318

1995

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Low-temperature processed MOSFETs with liquid phase deposited SiO/sub 2-x/F x as gate insulator

IEEE electron device letters, 1995-07, Vol.16 (7), p.316-318

1995

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Low-temperature processed MOSFETs with liquid phase deposited SiO(2-x)F(x) as gate insulator

IEEE electron device letters, 1995-07, Vol.16 (7), p.316-318

1995

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Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO(2) gate insulator

IEEE transactions on electron devices, 1994-02, Vol.41 (2), p.173-179

1994

Volltextzugriff (PDF)

Performance and off-state current mechanisms of low-temperature processed polysilicon thin-film transistors with liquid phase deposited SiO/sub 2/ gate insulator

IEEE transactions on electron devices, 1994-02, Vol.41 (2), p.173-179

1994

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Novel technique for SiO sub(2) formed by liquid-phase deposition for low-temperature processed polysilicon TFT

IEEE electron device letters, 1993-01, Vol.14 (8), p.403-405

1993

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Plasma damage during dielectric etch in high density plasma etcher

1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395), 1999, p.84-87

1999

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Compounding effects of UV exposure, ion bombardment, electron shading and plasma charging in a high density plasma poly etcher

1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395), 1999, p.41-44

1999

Volltextzugriff (PDF)

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Process sensitivity and robustness analysis of via-first dual-damascene process

Effects of plasma treatment on the properties of room-temperature liquid-phase deposited (LPD) oxide films

Thinner liquid phase deposited oxide for polysilicon thin-film transistors

Plasma charging damage during contact hole etch in high-density plasma etcher

Performance and off-state current mechanisms of low-temperature processed polysilicon thin-film transistors with liquid phase deposited SiO2 gate insulator

Low-Temperature-Processed Poly-Si Thin-Film Transistors Using Solid-Phase-Crystallized and Liquid-Phase-Deposited Gate Oxide

Stress in Liquid‐Phase Deposited Oxide Films

Low-temperature processed MOSFET's with liquid phase deposited SiO2-xFx as gate insulator

Novel technique for SiO2 formed by liquid-phase deposition for low-temperature processed polysilicon TFT

A 25-nm gate-length FinFET transistor module for 32nm node

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

Fabrication of MOSFETs using low-temperature liquid-phase deposited oxide

Narrow Width and Length Dependence of SiGe and Sallow-Trench-Isolation Stress Induced Defects in 45 nm p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Strained SiGe Source/Drain

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications

A test structure to verify the robustness of silicided N+/P+ interface

High quality thin oxide films formed by using ultra low temperature liquid phase deposition

Reverse CoSi 2 Thermal Stability and Digitized Sheet Resistance Increase of Sub-90 nm Polysilicon Lines

Low-temperature processed MOSFETs with liquid phase deposited SiO/sub 2-x/Fx as gate insulator

Low-temperature processed MOSFETs with liquid phase deposited SiO/sub 2-x/F x as gate insulator

Low-temperature processed MOSFETs with liquid phase deposited SiO(2-x)F(x) as gate insulator

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO(2) gate insulator

Performance and off-state current mechanisms of low-temperature processed polysilicon thin-film transistors with liquid phase deposited SiO/sub 2/ gate insulator

Novel technique for SiO sub(2) formed by liquid-phase deposition for low-temperature processed polysilicon TFT

Plasma damage during dielectric etch in high density plasma etcher

Compounding effects of UV exposure, ion bombardment, electron shading and plasma charging in a high density plasma poly etcher

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