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A Simulation Study for Typical Design Rule Patterns in 5 nm Logic Process with EUV Photolithographic Process

Journal of microelectronic manufacturing, 2019-12, Vol.2 (4), p.1-8

2019

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The Effect of Fin Structure in 5 nm FinFET Technology

Journal of microelectronic manufacturing, 2019-12, Vol.2 (4), p.1-8

2019

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Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography

Journal of microelectronic manufacturing, 2020-03, Vol.3 (1), p.1-8

2020

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Fast and Accurate Machine Learning Inverse Lithography Using Physics Based Feature Maps and Specially Designed DCNN

Journal of microelectronic manufacturing, 2020-12, Vol.3 (4), p.1-8

2020

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A Correlation-Considered Variation-Aware Interconnect Parasitic Profile Extraction Method

IEEE transactions on electron devices, 2012-09, Vol.59 (9), p.2321-2326

2012

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IEEE_Xplore

Cryogenic CMOS RF Device Modeling for Scalable Quantum Computer Design

IEEE journal of the Electron Devices Society, 2022, Vol.10, p.532-539

2022

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Fast and Robust DCNN Based Lithography SEM Image Contour Extraction Models

Journal of microelectronic manufacturing, 2021-03, Vol.4 (1), p.1-8

2021

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A Device Design for 5 nm Logic FinFET Technology

Journal of microelectronic manufacturing, 2020-03, Vol.3 (1), p.1-8

2020

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Air‐Stable and Self‐Driven Perovskite Photodiodes with High On/Off Ratio and Swift Photoresponse

Small (Weinheim an der Bergstrasse, Germany), 2018-10, Vol.14 (41), p.e1802764-n/a

2018

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Development and characterization of TaN thin film resistor with CMOS compatible fabrication process

2017 IEEE 12th International Conference on ASIC (ASICON), 2017, p.160-162

2017

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IEEE_Xplore

TCAD‐based statistical modeling methodology for nanoscale FinFET variability

Microwave and optical technology letters, 2021-08, Vol.63 (8), p.2097-2102

2021

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Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

MATEC Web of Conferences, 2015, Vol.22, p.2023

2015

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An Optimized Scalable BSIM Macromodel for HV Double-Diffused Drain MOSFET I-V Characteristics

IEEE transactions on power electronics, 2008-03, Vol.23 (2), p.1027-1030

2008

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An Optimized Scalable BSIM Macromodel for HV Double-Diffused Drain MOSFET - Characteristics

IEEE transactions on power electronics, 2008-03, Vol.23 (2), p.1027-1030

2008

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IEEE_Xplore

Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs

IEEE electron device letters, 2020-05, Vol.41 (5), p.661-664

2020

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IEEE_Xplore

Cryo-CMOS Model-Enabled 8-Bit Current Steering DAC Design for Quantum Computing

2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.3413-3417

2022

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IEEE_Xplore

MEMS micro-bridge structure-based process platform fabricated with CMOS Al BEOL compatible process

Japanese Journal of Applied Physics, 2019-07, Vol.58 (SH), p.SHHH02

2019

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Analytical long-term NBTI recovery model with slowing diffusivity and locking effect of hydrogen considered

Microelectronics and reliability, 2017-08, Vol.75, p.20-26

2017

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Analytical parameter extraction for NBTI reaction diffusion and trapping/detrapping models

Microelectronics and reliability, 2016-11, Vol.66, p.10-15

2016

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Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40nm technology

Solid-state electronics, 2015-09, Vol.111, p.118-122

2015

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Energy efficient and robust reservoir computing system using ultrathin (3.5 nm) ferroelectric tunneling junctions for temporal data learning

2021 Symposium on VLSI Technology, 2021, p.1-2

2021

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IEEE_Xplore

The Soft X-Ray Lithography Performance under Typical Single-digit nm Logic Design Rules, Including Stochastics and Defectivity

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020, p.1-3

2020

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Development of low stress TaN thin film for MEMS/sensor electrode application

2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC), 2012, p.1-3

2012

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IEEE_Xplore

Cu/Airgap integration on 90nm Cu BEOL process platform

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012, p.1-3

2012

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IEEE_Xplore

A BRIEF REVIEW OF SOURCE/DRAIN ENGINEERING IN CMOS TECHNOLOGY AND FUTURE OUTLOOK

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020, p.1-4

2020

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A Simulation Study for Typical Design Rule Patterns in 5 nm Logic Process with EUV Photolithographic Process

The Effect of Fin Structure in 5 nm FinFET Technology

Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography

Fast and Accurate Machine Learning Inverse Lithography Using Physics Based Feature Maps and Specially Designed DCNN

A Correlation-Considered Variation-Aware Interconnect Parasitic Profile Extraction Method

Cryogenic CMOS RF Device Modeling for Scalable Quantum Computer Design

Fast and Robust DCNN Based Lithography SEM Image Contour Extraction Models

A Device Design for 5 nm Logic FinFET Technology

Air‐Stable and Self‐Driven Perovskite Photodiodes with High On/Off Ratio and Swift Photoresponse

Development and characterization of TaN thin film resistor with CMOS compatible fabrication process

TCAD‐based statistical modeling methodology for nanoscale FinFET variability

Accurate SPICE Modeling of Poly-silicon Resistor in 40nm CMOS Technology Process for Analog Circuit Simulation

An Optimized Scalable BSIM Macromodel for HV Double-Diffused Drain MOSFET I-V Characteristics

An Optimized Scalable BSIM Macromodel for HV Double-Diffused Drain MOSFET - Characteristics

Temperature-Driven Gate Geometry Effects in Nanoscale Cryogenic MOSFETs

Cryo-CMOS Model-Enabled 8-Bit Current Steering DAC Design for Quantum Computing

MEMS micro-bridge structure-based process platform fabricated with CMOS Al BEOL compatible process

Analytical long-term NBTI recovery model with slowing diffusivity and locking effect of hydrogen considered

Analytical parameter extraction for NBTI reaction diffusion and trapping/detrapping models

Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40nm technology

Energy efficient and robust reservoir computing system using ultrathin (3.5 nm) ferroelectric tunneling junctions for temporal data learning

The Soft X-Ray Lithography Performance under Typical Single-digit nm Logic Design Rules, Including Stochastics and Defectivity

Development of low stress TaN thin film for MEMS/sensor electrode application

Cu/Airgap integration on 90nm Cu BEOL process platform

A BRIEF REVIEW OF SOURCE/DRAIN ENGINEERING IN CMOS TECHNOLOGY AND FUTURE OUTLOOK

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