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Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation

IEEE transactions on power electronics, 2022-03, Vol.37 (3), p.2970-2982

2022

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Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-12, Vol.41 (12), p.5515-5525

2022

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Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-08, Vol.40 (8), p.1626-1639

2021

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Organic Current Mirror PUF for Improved Stability Against Device Aging

IEEE sensors journal, 2020-07, Vol.20 (14), p.7569-7578

2020

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Surface-Potential-Based Silicon Carbide Power MOSFET Model for Circuit Simulation

IEEE transactions on power electronics, 2018-12, Vol.33 (12), p.10774-10783

2018

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Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit

Journal of electronic testing, 2020-08, Vol.36 (4), p.537-546

2020

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Statistical Extraction of Normally and Lognormally Distributed Model Parameters for Power MOSFETs

IEEE transactions on semiconductor manufacturing, 2020-05, Vol.33 (2), p.150-158

2020

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Feasibility of a low-power, low-voltage complementary organic thin film transistor buskeeper physical unclonable function

Japanese Journal of Applied Physics, 2019-04, Vol.58 (SB), p.SBBG03

2019

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Recovery-aware bias-stress degradation model for organic thin-film transistors considering drain and gate bias voltages

Japanese Journal of Applied Physics, 2020-04, Vol.59 (SG), p.SGGG08

2020

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Measurement and Modeling of Ambient-Air-Induced Degradation in Organic Thin-Film Transistor

IEEE transactions on semiconductor manufacturing, 2020-05, Vol.33 (2), p.216-223

2020

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Measurement and modeling of gate-drain capacitance of silicon carbide vertical double-diffused MOSFET

Japanese Journal of Applied Physics, 2017-04, Vol.56 (4S), p.4-04CR07

2017

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A Three-Level GaN Driver for High False Turn-ON Tolerance with Minimal Reverse Conduction Loss

IEEE open journal of power electronics, 2023-01, Vol.4, p.1-10

2023

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Mechanically and electrically robust metal-mask design for organic CMOS circuits

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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A compact model of I -V characteristic degradation for organic thin film transistors

2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS), 2019, p.194-199

2019

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Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage

2018 IEEE 27th Asian Test Symposium (ATS), 2018, p.167-172

2018

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Hardware–Software Co-Design for Decimal Multiplication

Computers (Basel), 2021-02, Vol.10 (2), p.17

2021

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A Variability-Aware Adaptive Test Flow for Test Quality Improvement

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-07, Vol.33 (7), p.1056-1066

2014

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A high power curve tracer for characterizing full operational range of SiC power transistors

2016 International Conference on Microelectronic Test Structures (ICMTS), 2016, p.90-94

2016

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Efficient parameter-extraction of SPICE compact model through automatic differentiation

2018 IEEE International Conference on Microelectronic Test Structures (ICMTS), 2018, p.35-40

2018

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Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

Journal of electronic testing, 2016-10, Vol.32 (5), p.601-609

2016

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IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination

IEICE Transactions on Information and Systems, 2014, Vol.E97.D(8), pp.2095-2104

2014

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Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

2016 IEEE 25th Asian Test Symposium (ATS), 2016, p.234-239

2016

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Device-Parameter Estimation through IDDQ Signatures

IEICE Transactions on Information and Systems, 2013/02/01, Vol.E96.D(2), pp.303-313

2013

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Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis

Japanese Journal of Applied Physics, 2022-05, Vol.61 (SC), p.SC1076

2022

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Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-6

2024

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Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation

Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation

Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling

Organic Current Mirror PUF for Improved Stability Against Device Aging

Surface-Potential-Based Silicon Carbide Power MOSFET Model for Circuit Simulation

Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit

Statistical Extraction of Normally and Lognormally Distributed Model Parameters for Power MOSFETs

Feasibility of a low-power, low-voltage complementary organic thin film transistor buskeeper physical unclonable function

Recovery-aware bias-stress degradation model for organic thin-film transistors considering drain and gate bias voltages

Measurement and Modeling of Ambient-Air-Induced Degradation in Organic Thin-Film Transistor

Measurement and modeling of gate-drain capacitance of silicon carbide vertical double-diffused MOSFET

A Three-Level GaN Driver for High False Turn-ON Tolerance with Minimal Reverse Conduction Loss

Mechanically and electrically robust metal-mask design for organic CMOS circuits

A compact model of I -V characteristic degradation for organic thin film transistors

Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage

Hardware–Software Co-Design for Decimal Multiplication

A Variability-Aware Adaptive Test Flow for Test Quality Improvement

A high power curve tracer for characterizing full operational range of SiC power transistors

Efficient parameter-extraction of SPICE compact model through automatic differentiation

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control

Device-Parameter Estimation through IDDQ Signatures

Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis

Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process

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