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In-operando x-ray topography analysis of SiC metal–oxide–semiconductor field-effect transistors to visualize stacking fault expansion motions dynamically during operations

Journal of applied physics, 2021-10, Vol.130 (14)

2021

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Non-destructive detection of sub-micrometer-sized micropipes in silicon carbide using mirror electron microscope

Journal of applied physics, 2023-11, Vol.134 (19)

2023

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Fabrication of 4H-SiC PiN diodes without bipolar degradation by improved device processes

Journal of applied physics, 2017-12, Vol.122 (24)

2017

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The Performance of Operational Amplifiers Consisting of 4H-SiC CMOS After Gamma Irradiation

IEEE transactions on electron devices, 2019-01, Vol.66 (1), p.343-348

2019

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Three-dimensional micro-X-ray topography using focused sheet-shaped X-ray beam

Scientific reports, 2023-07, Vol.13 (1), p.12381-12381, Article 12381

2023

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Modeling and Evaluation of Stacking Fault Expansion Velocity in Body Diodes of 3.3 kV SiC MOSFET

Journal of electronic materials, 2019-03, Vol.48 (3), p.1704-1713

2019

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Nucleation sites of expanded stacking faults detected by in operando x-ray topography analysis to design epitaxial layers for bipolar-degradation-free SiC MOSFETs

AIP advances, 2022-03, Vol.12 (3), p.035310-035310-12

2022

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Analysis of high reverse currents of 4H-SiC Schottky-barrier diodes

Journal of applied physics, 2017-12, Vol.122 (23)

2017

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Advanced X‐ray imaging at beamline 07 of the SAGA Light Source

Journal of synchrotron radiation, 2021-11, Vol.28 (6), p.1966-1977

2021

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Effect of trench structure on reverse characteristics of 4H-SiC junction barrier Schottky diodes

Japanese Journal of Applied Physics, 2017-12, Vol.56 (12), p.121301

2017

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Two-component model for long-term prediction of threshold voltage shifts in SiC MOSFETs under negative bias stress

Japanese Journal of Applied Physics, 2015-04, Vol.54 (4S), p.4-1-04DP12-5

2015

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Static and switching characteristics of 3.3 kV double channel-doped SiC vertical junction field effect transistor in cascode configuration

Japanese Journal of Applied Physics, 2015-04, Vol.54 (4S), p.4-1-04DP15-5

2015

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Direct Observation of Dielectric Breakdown at Step-Bunching on 4H-SiC

Materials science forum, 2015-06, Vol.821-823, p.468-471

2015

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Ultra-Shallow Junction Formation by Non-Melt Laser Spike Annealing and its Application to Complementary Metal Oxide Semiconductor Devices in 65-nm Node

Japanese Journal of Applied Physics, 2006-07, Vol.45 (7R), p.5708

2006

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Completely Quantum-Mechanical Extraction of Equivalent Oxide Thickness of PMOS Gate Insulator

IEEE transactions on electron devices, 2011-03, Vol.58 (3), p.650-657

2011

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Development of Wide-JFET Trench-Etched Double-Diffused MOS (TED-MOS) for High-Voltage Applications

IEEE transactions on electron devices, 2024-04, Vol.71 (4), p.2570-2576

2024

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Comparison of Extremely High-Temperature Characteristics of Planar and Three- Dimensional SiC MOSFETs

IEEE electron device letters, 2019-09, Vol.40 (9), p.1382-1384

2019

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Mechanism of Maximum-Current Limitation for 10-kV SiC-IGBT Module by Analyzing Surge Current Test Result

IEEE transactions on electron devices, 2023-10, Vol.70 (10), p.5210-5216

2023

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Power Loss Reduction of N-Channel 10-kV SiC IGBTs With Box Cell Layout

IEEE transactions on electron devices, 2023-07, Vol.70 (7), p.3768-3773

2023

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4H-SiC CMOS Transimpedance Amplifier of Gamma-Irradiation Resistance Over 1 MGy

IEEE transactions on electron devices, 2020-01, Vol.67 (1), p.224-229

2020

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Two Mechanisms of Charge Accumulation in Edge Termination of 4H-SiC Diodes Caused by High-Temperature Bias Stress and High-Temperature and High-Humidity Bias Stress

IEEE transactions on electron devices, 2018-08, Vol.65 (8), p.3318-3325

2018

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Device Design Consideration for Robust SiC VDMOSFET With Self-Aligned Channels Formed by Tilted Implantation

IEEE transactions on electron devices, 2019-08, Vol.66 (8), p.3447-3452

2019

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Electrical Characteristics of Large Chip-Size 3.3 kV SiC-JBS Diodes

Materials science forum, 2013-01, Vol.740-742, p.881-886

2013

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Failure of Switching Operation of SiC-MOSFETs and Effects of Stacking Faults on Safe Operation Area

IEEE transactions on electron devices, 2018-10, Vol.65 (10), p.4448-4454, Article 4448

2018

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Vertical-Channel Fin-SiC (VC Fin-SiC) With Partially Highly Doped JFET for 3.3-kV Applications

IEEE transactions on electron devices, 2024-09, Vol.71 (9), p.5559-5564

2024

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In-operando x-ray topography analysis of SiC metal–oxide–semiconductor field-effect transistors to visualize stacking fault expansion motions dynamically during operations

Non-destructive detection of sub-micrometer-sized micropipes in silicon carbide using mirror electron microscope

Fabrication of 4H-SiC PiN diodes without bipolar degradation by improved device processes

The Performance of Operational Amplifiers Consisting of 4H-SiC CMOS After Gamma Irradiation

Three-dimensional micro-X-ray topography using focused sheet-shaped X-ray beam

Modeling and Evaluation of Stacking Fault Expansion Velocity in Body Diodes of 3.3 kV SiC MOSFET

Nucleation sites of expanded stacking faults detected by in operando x-ray topography analysis to design epitaxial layers for bipolar-degradation-free SiC MOSFETs

Analysis of high reverse currents of 4H-SiC Schottky-barrier diodes

Advanced X‐ray imaging at beamline 07 of the SAGA Light Source

Effect of trench structure on reverse characteristics of 4H-SiC junction barrier Schottky diodes

Two-component model for long-term prediction of threshold voltage shifts in SiC MOSFETs under negative bias stress

Static and switching characteristics of 3.3 kV double channel-doped SiC vertical junction field effect transistor in cascode configuration

Direct Observation of Dielectric Breakdown at Step-Bunching on 4H-SiC

Ultra-Shallow Junction Formation by Non-Melt Laser Spike Annealing and its Application to Complementary Metal Oxide Semiconductor Devices in 65-nm Node

Completely Quantum-Mechanical Extraction of Equivalent Oxide Thickness of PMOS Gate Insulator

Development of Wide-JFET Trench-Etched Double-Diffused MOS (TED-MOS) for High-Voltage Applications

Comparison of Extremely High-Temperature Characteristics of Planar and Three- Dimensional SiC MOSFETs

Mechanism of Maximum-Current Limitation for 10-kV SiC-IGBT Module by Analyzing Surge Current Test Result

Power Loss Reduction of N-Channel 10-kV SiC IGBTs With Box Cell Layout

4H-SiC CMOS Transimpedance Amplifier of Gamma-Irradiation Resistance Over 1 MGy

Two Mechanisms of Charge Accumulation in Edge Termination of 4H-SiC Diodes Caused by High-Temperature Bias Stress and High-Temperature and High-Humidity Bias Stress

Device Design Consideration for Robust SiC VDMOSFET With Self-Aligned Channels Formed by Tilted Implantation

Electrical Characteristics of Large Chip-Size 3.3 kV SiC-JBS Diodes

Failure of Switching Operation of SiC-MOSFETs and Effects of Stacking Faults on Safe Operation Area

Vertical-Channel Fin-SiC (VC Fin-SiC) With Partially Highly Doped JFET for 3.3-kV Applications

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