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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

IEEE journal of solid-state circuits, 2001-05, Vol.36 (5), p.784-791

2001

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250 Mbps―5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μm CMOS

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2560-2570

2011

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Partial-response maximum-likelihood core development for a CD/DVD controller integrated circuit

IEEE transactions on magnetics, 2001-03, Vol.37 (2), p.663-669

2001

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250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 [Formula Omitted]m CMOS

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2560

2011

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250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 \mum CMOS

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2560-2570

2011

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An efficient global motion characterization method for image processing applications

IEEE transactions on consumer electronics, 1997-11, Vol.43 (4), p.1010-1018

1997

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A divide-by-16.5 circuit for 10-Gb ethernet transceiver in 0.13-μm CMOS

IEEE journal of solid-state circuits, 2005-05, Vol.40 (5), p.1175-1179

2005

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250Mbps-5Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13μm CMOS

2010 IEEE Asian Solid-State Circuits Conference, 2010, p.1-4

2010

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A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS

2007 IEEE Symposium on VLSI Circuits, 2007, p.234-235

2007

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A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.233-242

2006

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Fast locking clock generator using analog synchronous mirror delay technique with feedback control

2001 6th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.01EX443), 2001, Vol.2, p.1125-1127 vol.2

2001

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A Multiphase Delay-Locked Loop for 0.125-2Gbps 0.18/spl mu/m CMOS Transmitter

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers, 2006, p.35-36

2006

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Load-adaptive, low switching-noise output buffer

Electronics letters, 1999-06, Vol.35 (12), p.952-953, Article 952

1999

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The design of 16/spl times/16 wave pipelined multiplier using fan-in equalization technique

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1997, Vol.1, p.336-339 vol.1

1997

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A global motion characterization method using one-dimensional characteristic curves for image processing applications

1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997, Vol.2, p.1393-1396 vol.2

1997

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A load-adaptive, low switching-noise data output buffer

1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999, Vol.1, p.39-42 vol.1

1999

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A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103), 2000, p.50-51

2000

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An Advanced 2 Dimensional Y/C Separation And Y/C Processing VLSI For NTSC Composite Video Signal

IEEE 1992 International Conference on Consumer Electronics Digest of Technical Papers, 1992, p.256-257

1992

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A dual-loop delay-locked loop using multiple voltage-controlled delay lines

250 Mbps―5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μm CMOS

Partial-response maximum-likelihood core development for a CD/DVD controller integrated circuit

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 [Formula Omitted]m CMOS

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 \mum CMOS

An efficient global motion characterization method for image processing applications

A divide-by-16.5 circuit for 10-Gb ethernet transceiver in 0.13-μm CMOS

250Mbps-5Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13μm CMOS

A Dual PFD Phase Rotating Multi-Phase PLL for 5Gbps PCI Express Gen2 Multi-Lane Serial Link Receiver in 0.13um CMOS

A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control

Fast locking clock generator using analog synchronous mirror delay technique with feedback control

A Multiphase Delay-Locked Loop for 0.125-2Gbps 0.18/spl mu/m CMOS Transmitter

Load-adaptive, low switching-noise output buffer

The design of 16/spl times/16 wave pipelined multiplier using fan-in equalization technique

A global motion characterization method using one-dimensional characteristic curves for image processing applications

A load-adaptive, low switching-noise data output buffer

A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector

An Advanced 2 Dimensional Y/C Separation And Y/C Processing VLSI For NTSC Composite Video Signal

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