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Distribution of nanoscale nuclei in the amorphous dome of a phase change random access memory

Applied physics letters, 2014-02, Vol.104 (7)

2014

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Editorial Special Issue on "Memory Devices and Technologies for the Next Decade"

IEEE transactions on electron devices, 2020-04, Vol.67 (4), p.1369-1372

2020

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Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

IEEE transactions on electron devices, 2014-06, Vol.61 (6), p.2064-2070

2014

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Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

IEEE transactions on electron devices, 2016-03, Vol.63 (3), p.1047-1053

2016

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Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

IEEE journal of solid-state circuits, 2015-06, Vol.50 (6), p.1491-1501

2015

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A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

IEEE electron device letters, 2015-04, Vol.36 (4), p.330-332

2015

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Modeling and Characterization of Hydrogen-Induced Charge Loss in Nitride-Trapping Memory

IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1360-1365

2007

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Dynamic Resistance-A Metric for Variability Characterization of Phase-Change Memory

IEEE electron device letters, 2009-02, Vol.30 (2), p.126-129

2009

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A transient analysis method to characterize the trap vertical location in nitride-trapping devices

IEEE electron device letters, 2004-12, Vol.25 (12), p.816-818

2004

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Phase change materials and their application to random access memory technology

Microelectronic engineering, 2008-12, Vol.85 (12), p.2330-2333

2008

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Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs

Japanese Journal of Applied Physics, 2010-04, Vol.49 (4), p.04DD17-04DD17-4

2010

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High sensitive and wide detecting range MOS tunneling temperature sensors for on-chip temperature detection

IEEE transactions on electron devices, 2004-09, Vol.51 (9), p.1514-1521

2004

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An on-chip temperature sensor by utilizing a MOS tunneling diode

IEEE electron device letters, 2001-06, Vol.22 (6), p.299-301

2001

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Ultralow leakage characteristics of ultrathin gate oxides (/spl sim/3 nm) prepared by anodization followed by high-temperature annealing

IEEE transactions on electron devices, 2002-01, Vol.49 (1), p.179-181

2002

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Design and Implementation of SPEEX Speech Technology on ARM Processor

Mobile Internet Security, 2018, Vol.797, p.65-79

2018

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A Novel Ni/WOX/W Resistive Random Access Memory with Excellent Retention and Low Switching Current

Jpn J Appl Phys, 2011-04, Vol.50 (4), p.04DD11-04DD11-5

2011

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Study of localized tunnel oxide degradation after hot carrier stressing using a novel mid-bandgap voltage characterization method

2009 IEEE International Reliability Physics Symposium, 2009, p.294-300

2009

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A novel capacitive-coupled floating gate antenna protection design and its application to prevent in-process charging effects for 3D NAND flash memory

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014, p.1-2

2014

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Study of Charge Loss Mechanism of SONOS-Type Devices using Hot-Hole Erase and Methods to Improve the Charge Retention

2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.523-529

2006

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Improvement in the electrical properties of thin gate oxides by chemical-assisted electron stressing followed by annealing (CAESA)

IEEE electron device letters, 1999-11, Vol.20 (11), p.545-547

1999

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Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage

2013 Symposium on VLSI Technology, 2013, p.T156-T157

2013

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A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

2012 Symposium on VLSI Technology (VLSIT), 2012, p.91-92

2012

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A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure

2011 Symposium on VLSI Technology - Digest of Technical Papers, 2011, p.68-69

2011

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A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming

2013 Symposium on VLSI Technology, 2013, p.T152-T153

2013

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Distribution of nanoscale nuclei in the amorphous dome of a phase change random access memory

Editorial Special Issue on "Memory Devices and Technologies for the Next Decade"

Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices

Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

Modeling and Characterization of Hydrogen-Induced Charge Loss in Nitride-Trapping Memory

Dynamic Resistance-A Metric for Variability Characterization of Phase-Change Memory

A transient analysis method to characterize the trap vertical location in nitride-trapping devices

Phase change materials and their application to random access memory technology

Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs

High sensitive and wide detecting range MOS tunneling temperature sensors for on-chip temperature detection

An on-chip temperature sensor by utilizing a MOS tunneling diode

Ultralow leakage characteristics of ultrathin gate oxides (/spl sim/3 nm) prepared by anodization followed by high-temperature annealing

Design and Implementation of SPEEX Speech Technology on ARM Processor

A Novel Ni/WOX/W Resistive Random Access Memory with Excellent Retention and Low Switching Current

Study of localized tunnel oxide degradation after hot carrier stressing using a novel mid-bandgap voltage characterization method

A novel capacitive-coupled floating gate antenna protection design and its application to prevent in-process charging effects for 3D NAND flash memory

Study of the impact of charge-neutrality level (CNL) of grain boundary interface trap on device variability and P/E cycling endurance of 3D NAND flash memory

Study of Charge Loss Mechanism of SONOS-Type Devices using Hot-Hole Erase and Methods to Improve the Charge Retention

Improvement in the electrical properties of thin gate oxides by chemical-assisted electron stressing followed by annealing (CAESA)

Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure

A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming

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