UB Paderborn / Katalog / Suche / in CDI

Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design

IEEE transactions on computer-aided design of integrated circuits and systems, 2001-07, Vol.20 (7), p.813-827

2001

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Analog building block design in 14nm FinFET using inversion coefficient

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014, p.1-3

2014

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Canonical symbolic analysis of large analog circuits with determinant decision diagrams

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-01, Vol.19 (1), p.1-18

2000

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On symbolic model order reduction

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-07, Vol.25 (7), p.1257-1272

2006

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Multilevel symmetry-constraint generation for retargeting large analog layouts

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.945-960

2006

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Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2005-05, Vol.52 (5), p.975-993

2005

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Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-07, Vol.25 (7), p.1392-1400

2006

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SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1087-1103

2006

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Efficient approximation of symbolic expressions for analog behavioral modeling and analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2004-06, Vol.23 (6), p.907-918

2004

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Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-04, Vol.19 (4), p.401-412

2000

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Transition-Zone Mineral Assemblages in Peridotite Massifs, Tibet： Implications for Collision-zone Dynamics and Orogenic Peridotites

Acta geologica Sinica (Beijing), 2015-12, Vol.89 (s2), p.90-91

English ed., 2015

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Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes

IEEE transactions on circuits and systems. I, Regular papers, 2008-12, Vol.55 (11), p.3697-3710

2008

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Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-04, Vol.53 (4), p.892-904

2006

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Generalized Kirchoff's current and Voltage law formulation for coupled circuit-electromagnetic Simulation with surface Integral equations

IEEE transactions on microwave theory and techniques, 2004-07, Vol.52 (7), p.1673-1682

2004

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Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-05, Vol.27 (5), p.791-802

2008

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Low-power LDPC decoding based on iteration prediction

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.3041-3044

2012

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Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.1432-1435

Shi, C.-J R

2010

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IPRAIL—intellectual property reuse-based analog IC layout automation

Integration (Amsterdam), 2003-11, Vol.36 (4), p.237-262

2003

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CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-07, Vol.26 (7), p.1270-1282

2007

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Fast-yet-accurate PVT simulation by combined direct and iterative methods

International Conference on Computer Aided Design: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design; 06-10 Nov. 2005, 2005, p.495-501

2005

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Simulation of Closely Related Dynamic Nonlinear Systems With Application to ProcessaVoltageaTemperature Corner Analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2008-01, Vol.27 (5)

2008

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Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-03, Vol.22 (3), p.277-284

2003

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Developing device models

IEEE circuits and devices magazine, 2005-07, Vol.21 (4), p.6-11

2005

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Efficient DC fault simulation of nonlinear analog circuits

Proceedings of the conference on Design, automation and test in Europe, 1998, p.899-904

1998

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Automatic test generation of linear analog circuits under parameter variations

Proceedings of 1998 Asia and South Pacific Design Automation Conference, 1998, p.501-506

1998

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Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design

Analog building block design in 14nm FinFET using inversion coefficient

Canonical symbolic analysis of large analog circuits with determinant decision diagrams

On symbolic model order reduction

Multilevel symmetry-constraint generation for retargeting large analog layouts

Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications

Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation

SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings

Efficient approximation of symbolic expressions for analog behavioral modeling and analysis

Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams

Transition-Zone Mineral Assemblages in Peridotite Massifs, Tibet： Implications for Collision-zone Dynamics and Orogenic Peridotites

Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes

Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

Generalized Kirchoff's current and Voltage law formulation for coupled circuit-electromagnetic Simulation with surface Integral equations

Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach

Low-power LDPC decoding based on iteration prediction

Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology

IPRAIL—intellectual property reuse-based analog IC layout automation

CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits

Fast-yet-accurate PVT simulation by combined direct and iterative methods

Simulation of Closely Related Dynamic Nonlinear Systems With Application to ProcessaVoltageaTemperature Corner Analysis

Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling

Developing device models

Efficient DC fault simulation of nonlinear analog circuits

Automatic test generation of linear analog circuits under parameter variations

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