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Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors

IEEE transactions on circuits and systems. I, Regular papers, 2022-07, Vol.69 (7), p.2832-2844

2022

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A chopper amplifier with a low duty‐cycle sub‐sampling in the switched‐capacitor integrator for noise reduction

Electronics letters, 2023-04, Vol.59 (7), p.n/a

2023

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Fall Detection System Based on Point Cloud Enhancement Model for 24 GHz FMCW Radar

Sensors (Basel, Switzerland), 2024-01, Vol.24 (2), p.648

2024

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EEG Signal Epilepsy Detection With a Weighted Neighbor Graph Representation and Two-Stream Graph-Based Framework

IEEE transactions on neural systems and rehabilitation engineering, 2023-01, Vol.31, p.3176-3187

2023

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A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS

IEEE transactions on biomedical circuits and systems, 2020-08, Vol.14 (4), p.811-824

2020

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A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF

ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 2023, p.5-8

2023

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A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission

IEEE transactions on circuits and systems. II, Express briefs, 2020-05, Vol.67 (5), p.831-835

2020

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The spike gating flow: A hierarchical structure-based spiking neural network for online gesture recognition

Frontiers in neuroscience, 2022-11, Vol.16, p.923587

2022

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SSGCNet: A Sparse Spectra Graph Convolutional Network for Epileptic EEG Signal Classification

IEEE transaction on neural networks and learning systems, 2024-09, Vol.35 (9), p.12157-12171

2024

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A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation

IEEE journal of solid-state circuits, 2020-05, Vol.55 (5), p.1386-1400

2020

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A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS

IEEE journal on emerging and selected topics in circuits and systems, 2020-09, Vol.10 (3), p.283-294

2020

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iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric

IEEE journal on emerging and selected topics in circuits and systems, 2019-06, Vol.9 (2), p.346-357

2019

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A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain

IEEE journal of solid-state circuits, 2021-11, Vol.56 (11), p.3360-3374

2021

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Accelerating Distributed GNN Training by Codes

IEEE transactions on parallel and distributed systems, 2023-09, Vol.34 (9), p.2598-2614

2023

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Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications

IEEE transactions on circuits and systems. II, Express briefs, 2021-05, Vol.68 (5), p.1705-1709

2021

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SAIL: A Deep-Learning-Based System for Automatic Gait Assessment From TUG Videos

IEEE transactions on human-machine systems, 2022-02, Vol.52 (1), p.110-122

2022

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A 19- \mu W Blocker-Tolerant Wake-Up Receiver With - 90-dBm Energy-Enhanced Sensitivity

IEEE transactions on microwave theory and techniques, 2023-10, Vol.71 (10), p.1-16

2023

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DEMRL: Dynamic estimation meta reinforcement learning for path following on unseen unmanned surface vehicle

Ocean engineering, 2023-11, Vol.288, p.115958, Article 115958

2023

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AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, Vol.42 (9), p.2994-3006

2023

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A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction

Integration (Amsterdam), 2022-05, Vol.84, p.1-11

2022

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Analysis of Passive Charge Sharing-Based Segmented SAR ADCs

IEEE transactions on very large scale integration (VLSI) systems, 2020-05, Vol.28 (5), p.1195-1206

2020

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A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting

IEEE transactions on circuits and systems. II, Express briefs, 2017-05, Vol.64 (5), p.545-549

2017

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Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs

IEEE transactions on very large scale integration (VLSI) systems, 2019-09, Vol.27 (9), p.1977-1989

2019

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Saliency-based YOLO for single target detection

Knowledge and information systems, 2021-03, Vol.63 (3), p.717-732

2021

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A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR

2024 IEEE Custom Integrated Circuits Conference (CICC), 2024, p.1-2

2024

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Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors

A chopper amplifier with a low duty‐cycle sub‐sampling in the switched‐capacitor integrator for noise reduction

Fall Detection System Based on Point Cloud Enhancement Model for 24 GHz FMCW Radar

EEG Signal Epilepsy Detection With a Weighted Neighbor Graph Representation and Two-Stream Graph-Based Framework

A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS

A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF

A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission

The spike gating flow: A hierarchical structure-based spiking neural network for online gesture recognition

SSGCNet: A Sparse Spectra Graph Convolutional Network for Epileptic EEG Signal Classification

A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation

A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS

iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric

A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain

Accelerating Distributed GNN Training by Codes

Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications

SAIL: A Deep-Learning-Based System for Automatic Gait Assessment From TUG Videos

A 19- \mu W Blocker-Tolerant Wake-Up Receiver With - 90-dBm Energy-Enhanced Sensitivity

DEMRL: Dynamic estimation meta reinforcement learning for path following on unseen unmanned surface vehicle

AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices

A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction

Analysis of Passive Charge Sharing-Based Segmented SAR ADCs

A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting

Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs

Saliency-based YOLO for single target detection

A -104dBm-Sensitivity Receiver with Shared Wireless LO and Envelope-Tracking Mixer Achieving -46dB SIR

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