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BDD decomposition for delay oriented pass transistor logic synthesis

IEEE transactions on very large scale integration (VLSI) systems, 2005-08, Vol.13 (8), p.957-970

2005

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Sub-watershed prioritization of Koyna river basin in India using multi criteria analytical hierarchical process, remote sensing and GIS techniques

Physics and chemistry of the earth. Parts A/B/C, 2022-12, Vol.128, p.103219, Article 103219

2022

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Technology mapping algorithm targeting routing congestion under delay constraints

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-04, Vol.25 (4), p.625-636

2006

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A predictive distributed congestion metric with application to technology mapping

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-05, Vol.24 (5), p.696-710

2005

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Development and Testing of Different Models of Coconut Dehusker

International journal of current microbiology and applied sciences, 2018-08, Vol.7 (8), p.1024-1033

2018

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Routing With Constraints for Post-Grid Clock Distribution in Microprocessors

IEEE transactions on computer-aided design of integrated circuits and systems, 2010-02, Vol.29 (2), p.245-249

Shelar, R.S.

2010

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Decomposition of finite state machines for area, delay minimization

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040), 1999, p.620-625

1999

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Delay-optimal simultaneous technology mapping and placement with applications to timing optimization

2008 IEEE/ACM International Conference on Computer-Aided Design, 2008, p.101-106

2008

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An efficient algorithm for low power pass transistor logic synthesis

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, 2002, p.87-92

2002

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Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits

Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design, 2001, p.449-452

2001

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Orthogonal partitioning and gated clock architecture for low power realization of FSMs

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541), 2000, p.266-270

2000

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BDD decomposition for delay oriented pass transistor logic synthesis

Sub-watershed prioritization of Koyna river basin in India using multi criteria analytical hierarchical process, remote sensing and GIS techniques

Technology mapping algorithm targeting routing congestion under delay constraints

A predictive distributed congestion metric with application to technology mapping

Development and Testing of Different Models of Coconut Dehusker

Routing With Constraints for Post-Grid Clock Distribution in Microprocessors

Decomposition of finite state machines for area, delay minimization

Delay-optimal simultaneous technology mapping and placement with applications to timing optimization

An efficient algorithm for low power pass transistor logic synthesis

Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits

Orthogonal partitioning and gated clock architecture for low power realization of FSMs

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